AD7606B Platform FPGA Architecture Control

The axi_ad7616_control module is connected to up_axi interface which receive register read / write command on its given below register map. It periodically generates start of conversion signal cnvst through timer based on the value in reg REG_UP_CONV_RATE and when enabled through REG_UP_CNTRL reg CNVST_EN and RESETN bit. In response ADC generates busy in signal which axi_ad7616_control receives and create a pulse at falling edge of busy signal to generate a end_of_conv that act as trigger for serial/parallel interface data capturing. up_read_req and up_write_req is given to axi_ad7616_pif for generating rd_n and wr_n signal for parallel interface. up_write_data send register write data over parallel bus to AD7606B whereas up_read_data along with up_read_valid receives register read data from ad7606B. It also act as hardware switch for parallel interface when IF_TYPE parameter is set as 1.

Files

Name	Description
axi_ad7616_control.v	Verilog source

Interface parameters

Name	Description
IF_TYPE	Selecting the interface for ADC, 0 for serial interface, 1 for parallel interface
ID	Core ID, it can be used in case of multiple cores on a system 0

Memory Map Registers

If the SPI engine is active from offset 0x0000 can be found the SPI engine memory space. The following register space is active in both PARALLEL and SERIAL mode.

Address DWORD BYTE	Bits	Name	Type	Description
0x0100 0x0400		REG_VERSION		Version and Scratch Registers
	[31:0]	VERSION[31:0]	RO	Version number
0x0101 0x0404		REG_ID		Version and Scratch Registers
	[31:0]	ID[31:0]	RO	Instance identifier number
0x0102 0x0408		REG_SCRATCH		Version and Scratch Register
	[31:0]	SCRATCH[31:0]	RW	Scratch register
0x0103 0x040C		REG_IF_TYPE		ADC Interface Control & Status
	[31:0]	IF_TYPE	RO	Actual interface type, if 0 SERIAL interface is active, PARALLEL otherwise
0x0110 0x0440		REG_UP_CNTRL		ADC Interface Control & Status
	[0]	RESETN	RW	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core
	[1]	CNVST_EN	RW	Enable the CNVST pulse generator of core
0x0111 0x0444		REG_UP_CONV_RATE		ADC Interface Control & Status
	[31:0]	UP_CONV_RATE	RW	Rate of the conversion pulse signal, it's relative to the system clock (s_axis_clk)
0x0112 0x0448		REG_UP_BURST_LENGTH		ADC Interface Control & Status
	[4:0]	UP_BURST_LENGTH	RW	Define the actual burst length. The value must be equal to burst length - 1 . This register is active just on PARALLEL mode
0x0113 0x044C		REG_UP_READ_DATA		ADC Interface Control & Status
	[31:0]	UP_READ_DATA	RO	This register can be used to read the device registers on PARALLEL software mode
0x0114 0x0450		REG_UP_WRITE_DATA		ADC Interface Control & Status
	[31:0]	UP_WRITE_DATA	WO	This register can be used to write the device registers on PARALLEL software mode

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