Golden Hardware Reference Design

Golden Hardware Reference Design

The Golden Hardware Reference Design (GHRD) for the DataStorm DAQ Board provides a starter reference design. It includes a Platform Designer reference design that maps a number of HDL based FPGA peripherals to the HPS (Hard Processor System) and the ARM Cortex-A9 processors. This design is intended as a starting point for new designs.

The user can either Create the Design from scratch or Use the Completed Design

Table of Contents

1. Overview
2. Create the Design
   1. Acquiring top-level files
   2. Creating project framework
   3. Creating Processor System
   4. Adding display IP
   5. Adding other Peripherals
   6. Creating top-level design
3. Use the Completed Design

Overview

The Golden Hardware Reference Design is an important part of the GSRD and consists of the following components:

• ARM Cortex®-A9 MPCore HPS
• HDMI Video output
• One user push-button inputs
• Two user DIP switch inputs
• Two user I/O for LED outputs
• JTAG UART
• System ID

Resources

• Quartus Info
• Quartus Intro video
• Platform Designer
• Scripting
• Design Constraints
• Design Compilation
• Design Optimization
• Design Recommendations
• Programming Intel FPGAs
• Debug Tools
• Cyclone V HPS Technical Reference Manual
• Cyclone V Overview
• Cyclone V Datasheet
• Cyclone V Handbook
• Cyclone V Transceivers
• Intel FPGA Training Courses

MPU Address Maps

This section presents the address maps as seen from the MPU (A9) side.

Lightweight HPS-to-FPGA Address Map

The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address 0xFF20_0000, is listed in the following table.

Periheral	Address Offset	Size (bytes)	Attribute
sys_id	0x1_0000	8	Unique system ID
button_pio	0x1_0020	16	DIP switch input
dipsw_pio	0x1_0030	16	Push button input
led_pio	0x1_0040	16	LED output display
axi_dmac_0	0x9_0000	2K	HDMI DMA Controller
axi_hdmi_tx_0	0xA_0000	64K	HDMI Transmit IP

Interrupt Routing

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupts from soft IP peripherals to the HPS interrupt input interface.

Periheral	Interrupt Number	Attribute
jtag_uart	f2h_irq0/1[0]	JTAG UART
button_pio	f2h_irq0/1[1]	1 push button (either level)
dipsw_pio	f2h_irq0/1[2]	8 DIP switch inputs (falling edge)
axi_dmac_0	f2h_irq0/1[4]	Video DMA Controller

When Creating the Design, a full build should take between 25 to 60 minutes.

The build will produce the following items:

File	Description
.sof	SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
Handoff	Folder containing a description of the hardware to be used by the Preloader Generator

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Next - Create the Design

Return to DataStorm DAQ GSRD Documentation
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