AD7606B Platform FPGA Architecture pack

The ad7606b_pack module receives 8 channels of 16-bit adc_data_n along with their individual adc_valid_n signals and packs them into a single 128-bit bus.

The packing is dependent on which channels are enabled. The enables are driven from memory-mapped registers in the axi_ad7606b_adc module.

Below, are examples of packing ADC data.

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