AD7768 Platform FPGA Architecture ad7768 if

AD7768 IF

The Analog Devices' AD7768 is an 8-channel simultaneous-sampling sigma-delta (Σ-Δ) analog-to-digital converter (ADC), with a Σ-Δ modulator and digital filter per channel, enabling synchronized sampling of ac and dc signals.
(For detailed operation and specifications refer to the datasheet.)

The interface for the AD7768's digital host is the ad7768_if module in the Cyclone V FPGA. The block diagram is shown here:

This module receives 8 channels of conversion data from the AD7768 on the data_in bus. This data is synchronous to clk_in and framed by ready_in.

Files ?

Name	Description
ad7768_if.v	Verilog source

Interface Signals

Name	Description
data_in[7]	ADC conversion Data In 7 ([note][2])
data_in[6]	ADC conversion Data In 6 ([note][3])
data_in[5:0]	ADC conversion Data In 5 down to 0
ready_in	Data Ready In. A periodic signal framing the conversion results from the eight ADC, synchronous to clk_in and data_in[7:0]
clk_in	ADC Conversion Data Clock. Clocks conversion data from the AD7768 to the digital host (FPGA)). It is synchronous with ready_in and any conversion data signal on data_in[7:0] derived from the MCLK signal (not on the FPGA).
adc_valid
adc_clk
adc_data[31:0]	Interleaved/sequenced adc channel data
up_status_clk[35:0]
up_crc_enable
up_crc_4_or_16_n
up_format[1:0]	Format Selection. These signals set the number of conversion data signals(data_in) used to output ADC conversion data.
up_sshot

Theory of Operation

Data interface

The data interface format is determined by the up_format signals. The logical state of FORMATx on the AD7768 is read on power- up and determines how many data lines (data_in) the ADC conversions are received on. Because the FORMATx pins are read on power-up of the AD7768 and the device remains in this output configuration, this function must always be hardwired and cannot be altered dynamically. Table 33, Figure 95, Figure 96, and Figure 98 show the formatting configuration for the digital output pins on the

up_format Truth Table

up_format1	up_format[0]	Description
0	0	Each ADC channel is on its own dedicated signal. data_in[7] and data_in[6] are in use.
0	1	The ADCs share data_in[0] and data_in1 signals. Channel 0 to channel 3 are on data_in[0]. Channels 4 to 7 are on data_in1. The ADC channels are time-division multiplexed (TDM) on the inputs. data_in[7] and data_in[6] are in use.
1	X	All channels TDM'd on data_in[0]. Only data_in[0] is in use.