AD7768 Platform FPGA Architecture ad7768 if

AD7768 I/F

The Analog Devices' AD7768 is an 8-channel simultaneous-sampling sigma-delta (Σ-Δ) analog-to-digital converter (ADC), with a Σ-Δ modulator and digital filter per channel, enabling synchronized sampling of ac and dc signals.
(For detailed operation and specifications refer to the datasheet.)

The interface for the AD7768's digital host is the ad7768_if module in the Cyclone V FPGA. The block diagram is shown here:

This module receives 8 channels of conversion data from the AD7768 on the data_in bus. This data is synchronous to clk_in and framed by ready_in.

Files

Name	Description
ad7768_if.v	Verilog source

Interface Signals

Name	Description
data_in[7]	ADC conversion Data In 7 (note)
data_in[6]	ADC conversion Data In 6 (note)
data_in[5:0]	ADC conversion Data In 5 down to 0
ready_in	Data Ready In. A periodic signal framing the conversion results from the eight ADCs, synchronous to clk_in and data_in[7:0]
clk_in	ADC conversion data clock. Clocks the conversion data from the AD7768 to the digital host (FPGA). It is synchronous with ready_in and any conversion data signal on data_in[7:0] derived from the MCLK signal (on AD7768), as either 1/2, 1/4, 1/8, or full rate clock.
adc_valid	Channel data valid, interleaved and aligned
adc_clk	ADC conversion data clock, from clk_in reassigned
adc_data[31:0]	Interleaved/sequenced and aligned ADC channel data, sent to the embedded ad7768 dma controller
up_status_clr[35:0]	Channel Status Clear
up_status[35:0]	Channel Status (gated by an enable and valid)
up_crc_enable	Enable Cyclic Redundancy Check, when in SPI control mode
up_crc_4_or_16_n	Indicates CRC message per channel every 4 samples when high, every 16 samples when low
up_format[1:0]	Format Selection. These signals set the number of conversion data signals(data_in) used to output ADC conversion data.
up_sshot	Single-shot mode. One-shot mode conversion mode operation when high. Standard conversion mode otherwise.

note

This signal is synchronous to clk_in and framed by ready_in. When up_format is set to 01, 10, or 11, and daisy-chaining is not used, connect this signal is unused.

Theory of Operation

Data interface

The data_in[7:0] bus is actually a serial data interface from the AD7768 on the evaluation board. The eval board outputs conversion results across the FMC connector, which are received on data_in[0] to data_in[7].. The serial data interface also includes signals such as clk_in and ready_in.

The data interface format is determined by the up_format signals. The logical state determines how many data lines (of data_in[7:0]) the ADC conversions are received on. Each ADC can be assigned a data_in[n] signal, or, the data can share the data_in signals in a time-division-multiplexed manner. The truth table below shows the formatting configuration for these signals.

up_format Truth Table

up_format1	up_format[0]	Description
0	0	Each ADC channel is on its own dedicated signal. data_in[7] and data_in[6] are in use.
0	1	The ADCs share data_in[0] and data_in1 signals. Channel 0 to channel 3 are on data_in[0]. Channels 4 to 7 are on data_in1. The ADC channels are time-division multiplexed (TDM) on the inputs. data_in[7] and data_in[6] are in use.
1	X	All channels TDM'd on data_in[0]. Only data_in[0] is in use.

Standard Mode Operation Data

In standard mode operation, the AD7768 operate as the primary device and streams data to the FPGA. The AD7768 supplies the data, the data clock (clk_in), and a falling edge framing signal (ready_in) to the secondary device. All of these signals are synchronous. The data interface connections to the FPGA are shown in the FPGA block diagram on the FPGA Architecture page. The up_format pins determine how the data is output from the AD7768.

The ready_in input is asserted one clock cycle before the MSB of the data conversion is made available on the data pin. Each ready_in falling edge starts the output of the new ADC conversion data. The first eight bits output after the ready_in falling edge are the header bits; the last 24 bits are the ADC conversion result.

Each ADC result comprises 32 bits. The first eight bits are the header status bits, which contain status information and the channel number. The names of each of the header status bits and their functions are explained in the AD7768 datasheet. This header is followed by a 24-bit ADC output in twos complement coding with MSB first. This data is output on the adc_data bus to the embedded DMA block.

One-Shot Mode Operation Data

One-shot mode is available in both SPI and pin control modes. In one-shot mode, the AD7768 is a pseudo secondary device. Conversions occur on request by the primary device, for example the Cyclone V FPGA.

In one-shot mode, all ADCs run continuously; however, the rising edge of the SYNC_IN pin on the AD7768 controls the point in time from which data is received. To receive data, the FPGA must pulse the SYNC_IN pin via GPIOs to reset the filter and force ready_in low. ready_in subsequently goes high to indicate to the primary device that the device has valid settled data available. Unlike standard mode, ready_in remains high for the number of clock periods of valid data before it goes low again. In this conversion mode, it is an active high frame of the data. For more details of the AD768 operation refer to the datasheet referenced earlier.

CRC

The AD7768 delivers 32 bits per channel as standard, which by default consists of 8 status header bits and 24 bits of data. However, there is also the option to employ a CRC check on the ADC conversion data. This functionality is available only when operating in SPI control mode. When employed, the CRC message is calculated on a per channel basis. The CRC then replaces the 8-bit header every four samples or every 16 samples.
An 8-bit CRC polynomial used is to calculate the CRC message: x^8 + x^2 + x + 1.

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