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PR Digest 58
Tiotto, Ettore edited this page Jun 2, 2026
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Period: 2026-05-24 to 2026-06-06 (Iteration 58) | Total PRs: 62 (32 from Xe2/Xe3/Xe3P, 30 from Xe4) | Lines changed: +61,272 / -11,495
The team delivered a new cache-residency optimization that keeps matrix-multiply operands in fast L1 cache across loop iterations, alongside notable math-performance wins: FP8-to-BF16 conversion is up to 59% faster and new fast sine/cosine functions match NVIDIA's speed. Several robustness fixes hardened the 2D block-load path against hardware limits and a wrong-results regression on the CRI simulator, and a compiler crash on deeply-nested conditionals was resolved. Two upstream synchronizations were completed with a 99.06% test pass rate.
Key accomplishments:
- Delivered a cache-residency optimization that keeps matrix-multiply operands resident in L1 across the inner loop, cutting redundant memory traffic
- Sped up FP8-to-BF16 conversion by up to 59% and added faster sine/cosine math functions matching NVIDIA's precision and performance contract
- Hardened the 2D block-load path against a 24-bit hardware pitch limit and an invalid-layout regression that produced wrong results on the CRI simulator
- Fixed a compiler crash on deeply-unrolled conditionals by aligning the layout-conversion cleanup with upstream
- Advanced CRI (Xe3P) enablement and migrated benchmarks off the deprecated XE-TLA library
- Maintained alignment with upstream Triton through two synchronizations at a 99.06% pass rate
New cache-control promotion, 2D block I/O hardware-limit guards, and atomic/shuffle lowering for Intel GPUs.
- #7059 Support for ttg.local_atomic_scatter_rmw lowering — Adds Gluon lowering for scatter read-modify-write, reusing the NVIDIA backend's path with 16-bit emulation. (+228/-38, @mieshkiwrk) — Fixes #6836
- #6978 EVICT_LAST promotion for known-reuse dot-fed loads — Promotes loads to evict_last when four reuse gates pass, keeping DPAS operands resident in L1 across the K-loop. (+478/-66, @etiotto) — Closes #6981
- #7036 Skip block IO when surface pitch exceeds 24-bit hardware limit — Disables 2D block loads in LowerTo2DBlockLoad when the surface pitch exceeds the 24-bit hardware limit. (+98/-4, @dev-tomek)
- #7044 Skip 1D->2D reshape when block IO for all layouts is disabled — Fixes a ~99% wrong-value regression by skipping the 1D→2D reshape load/store path when block IO is disabled on the simulator. (+95/-0, @etiotto) — Closes #6897
- #7032 Skip block IO when surface pitch exceeds 24-bit hardware limit — Returns a null pitch in MaterializeBlockPointer past the 24-bit limit, falling back to vectorized lowering and avoiding a verifier crash. (+119/-2, @dev-tomek) — Addresses #7022
- #7020 Add TritonGen Op SubGroupBitcastShuffle — Adds the SubGroupBitcastShuffle operation to the TritonGen dialect. (+100/-6, @chengjunlu)
- #6985 Extend ReuseAnalysis umbrella with knownReuse helper — Adds a knownReuse helper that requires positive spatial or temporal reuse proof, suitable for callers that force an action. (+140/-0, @etiotto)
Faster low-precision conversion and transcendental math functions for Intel GPUs.
- #7040 Replace FP8E4M3FN→BF16 table-lookup with single fmul rebias — Swaps a 100-op subnormal-table chain for a 42-op i16-mask plus bf16 fmul rebias, cutting latency up to 59% and staying bit-exact across all 256 byte values. (+181/-74, @etiotto) — Closes #7039
- #7064 Add fast_sinf and fast_cosf to Intel libdevice — Adds fast_sinf/fast_cosf lowering to the IMF _la tier, ~1.5x faster than tl.sin/tl.cos at ~1.8 ULP. (+110/-0, @etiotto) — Closes #7063
- #7012 Use -cl-fp32-correctly-rounded-divide-sqrt for LTS — Enables correctly-rounded fp32 divide/sqrt on LTS drivers (counterpart of #7006). (+55/-1, @anmyachev)
- #7006 Use -cl-fp32-correctly-rounded-divide-sqrt for LTS — Adds the correctly-rounded fp32 divide/sqrt build flag for LTS drivers. (+55/-1, @anmyachev)
Layout-conversion pass robustness and removal of an invalid IR transform.
- #7011 Split cleanup phase; tolerate SCF non-convergence — Splits RemoveLayoutConversions cleanup so SCF canonicalization is best-effort, fixing a compile crash on deeply-unrolled scf.if ladders (port of upstream PR #10132). (+14/-6, @etiotto)
- #6991 Revert invalid tt.local_alloc changes for i1 type — Reverts the i1-type tt.local_alloc changes that were determined to be invalid. (+11/-116, @chengjunlu)
2 upstream merges from OpenAI Triton (commits 2c873e5, ac7445b) — pass rate 99.06%.
Benchmark migration to SYCL-TLA, CRI/Windows test enablement, dependency upgrades, and CI build fixes.
- #7065 Use perf_counter_ns for compile timing — Switches CompileTimer to perf_counter_ns, fixing a Windows test broken by time.time()'s 16ms resolution. (+13/-9, @ksmoliansky) — Fixes #5665
- #6879 Replace XE-TLA with SYCL-TLA generic gemm + OneDNN — Migrates the GEMM benchmark off the deprecated XE-TLA to SYCL-TLA + OneDNN. (+11/-15, @slawblauciak)
- #6883 Add SYCL-TLA Split-K GEMM benchmark — Adds a SYCL-TLA Split-K GEMM benchmark. (+220/-24, @slawblauciak)
- #7057 Fallback to CPU for kernels with SYCL issues on CRI — Falls back to CPU execution for kernels that hit SYCL issues on the CRI simulator. (+9/-6, @chengjunlu)
- #6882 Remove XE-TLA references from fused_softmax — Removes deprecated XE-TLA references from the fused softmax benchmark. (+4/-14, @slawblauciak)
- #7038 Sync model list from torch-xpu-ops — Syncs the end-to-end model list from torch-xpu-ops. (+11/-0, @anmyachev)
- #7031 Add dynamic input size adjustment for CRI — Adds dynamic input-size adjustment for CRI (main-branch counterpart). (+10/-6, @whitneywhtsang)
- #7010 Update vLLM XPU translator script and mamba skiplist — Updates the vLLM XPU translator script and mamba skiplist. (+14/-1, @sarah12121212)
- #7008 Add patch to fix failing test_selective_state_update — Adds a patch fixing the failing mamba test_selective_state_update test. (+19/-2, @sarah12121212)
- #7014 Fix CI issues on release branch — Fixes CI issues on the release branch for the oneAPI 2026.0 switch. (+4/-67, @anmyachev)
- #7015 Add dynamic input size adjustment for CRI — Adds dynamic input-size adjustment to the CRI tutorials. (+43/-15, @whitneywhtsang)
- #7019 Fix spirv-dis build for PredicatedIOINTEL support — Always builds spirv-dis from source to get SPV_INTEL_predicated_io support after the DLE 2026.0.0 upgrade. (+1/-12, @whitneywhtsang)
- #6997 Sync third_party/amd files with upstream c7391a2 — Syncs the third_party/amd files with upstream commit c7391a2. (+1/-20, @etiotto)
- #6954 Fix test_device_assert_barrier crash on BMG with --forked — Fixes the test_device_assert_barrier crash on BMG when running with --forked. (+29/-11, @januszjah) — #6819
- #6990 WA for unified attention BMG OOM failures — Works around unified-attention out-of-memory failures on BMG in vLLM. (+11/-0, @dev-tomek) — #6759
- #6924 Add inductor cooperative reductions test and align Windows suite — Adds the inductor cooperative-reductions test and aligns the Windows test suite with Linux. (+36/-42, @anmyachev)
- #6995 Add NVL archs — Adds NVL architecture support. (+11/-0, @anmyachev)