PR Digest Iteration 67

PR Summary

Period: 2026-09-27 to 2026-10-10 (Iteration 67) | Total PRs: 18 (Xe2/Xe3/Xe3P) | Lines changed: +7,723 / -1,689

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Triton XPU BE (Xe2/Xe3/Xe3P) (18 PRs, +7,723 / -1,689)

The team fixed several ways the tensor descriptor load path could return wrong data or build malformed hardware loads. These cases now either get correct results or fall back safely to the regular load path. The register spill policy was retuned so heavily spilling kernels are rebuilt with a larger register file, and the CRI platform now runs the same full test workloads as the other targets. Two upstream synchronizations were completed with a test pass rate of about 98.9%.

Key accomplishments:

• Closed correctness gaps in tensor descriptor loads that could silently return shifted data, wrong padding values, or malformed hardware block loads
• Made the large-register-file rebuild trigger consistent across execution widths, so kernels that spill heavily recover their performance (also backported to the 3.9.0 release)
• Moved generated FP4 conversions onto the standardized industry encoding and fixed half-precision conversions on the long-term-support driver
• Restored full-size test coverage on CRI and made the vLLM benchmarks runnable on NVIDIA hardware for side-by-side comparison
• Stayed aligned with upstream Triton through two synchronizations (about 98.9% pass rate)

Tensor Descriptor Correctness

Fixes to how descriptor loads are lowered, so that inputs the fast path can't handle get correct results or fall back safely.

• #8087 Fold the load-time index into the gather-fallback vector width — Accounts for the access index's alignment when choosing the fallback vector width, so an odd 16-bit index no longer produces a misaligned wide load that returns shifted data. (+144/-27, @aditzhaki)
• #8178 Range-check descriptor load height, width and pitch before 2D block lowering — Checks that height, width and pitch fit the 24-bit hardware fields, with overflow-safe multiplication, and falls back to the gather path when they don't. (+603/-59, @etiotto)
• #8172 Fix wrong fill value for descriptors with mixed padding — Loads that can come from descriptors with different padding (zero vs NaN) are now lowered through pointers so each gets its requested fill value instead of silently getting zero. (+1539/-92, @etiotto)
• #8180 Bail out of row_major block_io on a non-unit last descriptor stride — Replaces an assert with a bail-out to the gather lowering, fixing a debug-build abort and a wrong 2D block path in release builds. (+71/-31, @etiotto)

Code Generation & Runtime

Changes to the register-file policy, conversion builtins, hardware workarounds and the launcher.

• #8081 Derive 02-fused-softmax occupancy from device properties — Exposes threads-per-EU and EUs-per-subslice from Level Zero and uses them in place of hardcoded Xe-HPC/Xe2 constants; closes #4413. (+35/-8, @Niz13)
• #8175 Use the OCP fp4 conversion builtins instead of the INTEL ones — Emits the EXT spelling of the FP4 conversion builtins so generated SPIR-V requires the standardized OCP microscaling extension. (+10/-10, @whitneywhtsang)
• #8217 Rebuild at large GRF once spilling reaches 1024 B per hardware thread — Backport of #8147 to the release/3.9.0 branch. (+250/-111, @whitneywhtsang)
• #8207 Fix bf16 <-> f16 conversions — Fixes bf16/f16 conversions on the LTS driver. (+108/-20, @anmyachev)
• #8147 Rebuild at large GRF once spilling reaches 1024 B per hardware thread — Replaces the per-lane spill-slot limit with a fixed 1024 B per hardware thread, so the large-GRF rebuild trigger no longer doubles at SIMD32; fixes #8077. (+250/-111, @etiotto)
• #7973 Explicitly pack dp4a registers — Works around an IGC bug that packs dp4a registers incorrectly (#7854). (+290/-2, @slawblauciak)
• #8158 Fix uninitialized read and leak of the zeModuleCreate build log — Initializes and always destroys the Level Zero module build-log handle in the launcher. (+7/-2, @aditzhaki)

Upstream Alignment

2 upstream merges from OpenAI Triton (commits 92d654e, edeea66) — pass rate 98.9–98.92%.

Test & CI Reliability

Wider test coverage on CRI, cross-vendor benchmarks, and dependency updates.

• #8085 Enable vLLM benchmarks to run on NVIDIA GPU — Makes the vLLM Triton kernel benchmarks device-agnostic so the same scripts run on XPU and NVIDIA; closes #7907. (+95/-24, @dudilester)
• #8114 Gate Eagle3 tests on XPU memory capacity — Runs the Eagle3 speculator test only on devices with at least 16 GB and removes it from the skip list; closes #7437. (+18/-3, @sarah12121212)
• #7879 Add torchao to nightly builds and local builds — Builds and publishes a torchao wheel pinned from PyTorch's commit pins, and adds it to local-build tooling; part of #7457. (+18/-5, @aditzhaki)
• #8218 Run full test and tutorial workloads on CRI — Removes CRI-only reductions (smaller shapes, iteration counts, autotune spaces, CPU fallbacks, xfails) so CRI runs the same workloads as other targets. (+56/-198, @whitneywhtsang)
• #8184 Update pin to pick up new pin of vllm-xpu-kernels release — Bumps the vLLM pin to pick up the new vllm-xpu-kernels release, with no perf impact on B580 CI; closes #8117. (+20/-1, @quinnlp)