PR Digest Iteration 59

PR Summary

Period: 2026-06-07 to 2026-06-20 (Iteration 59) | Total PRs: 63 (50 from Xe2/Xe3/Xe3P, 13 from Xe4) | Lines changed: +51,234 / -33,602

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Triton XPU BE (Xe2/Xe3/Xe3P) (50 PRs, +5,275 / -5,699)

The sprint delivered substantial advances across the memory access and compiler optimization stacks. A major feature landed enabling 2D block loads for tensors with runtime row strides, expanding hardware-accelerated memory access to more kernel configurations. The mask removal pass gained new predicate coverage and a fix for map poisoning. FP8-to-FP16 conversion was rewritten from a software table-lookup to a single hardware fused multiply, eliminating a major inference bottleneck. A new fast-math-gated floating-point reassociation pass was added to enable dot-scale hoisting in vLLM flash attention. Six upstream synchronizations were completed with a 99.5% test pass rate.

Key accomplishments:

• Enabled 2D block hardware loads for tensors with runtime row strides, widening the class of kernels that benefit from block I/O
• Made the layout optimization pipeline aware of 2D block encoding costs and enabled single-use load rematerialization, both reducing layout-induced performance regressions
• Reduced FP8 inference overhead by replacing a software 880-operation table-lookup with a single hardware fused multiply
• Extended RemoveMasks with new predicate support and a fix for multi-mask map corruption, broadening dead-mask elimination coverage
• Added fast-math-gated FP reassociation to unlock dot-scale hoisting in vLLM unified attention kernels
• Maintained full upstream alignment with a 99.5% pass rate across six synchronizations

Memory Access & Lowering

Improvements to 2D block I/O lowering, tensor descriptor load/store correctness, SPIR-V vs GenISA path selection, and hardware math instruction lowering.

• #6974 Enable 2D block load for runtime row strides — Adds support for 2D block hardware loads when the row stride is a runtime value, enabling block I/O in more matrix kernel configurations. (+545/-54, @wdziurdz)
• #7136 Use SPV_INTEL_rounded_divide_sqrt for precise math lowering — Lowers division and sqrt to the SPIR-V rounded-divide-sqrt extension, improving numerical precision on non-fast-math paths. (+74/-13, @whitneywhtsang)
• #7186 Use GenISA for unsupported SPV 2D block read — Falls back to GenISA intrinsics for 2D block read operations whose signatures are unsupported by the SPIR-V builtin interface. (+12/-0, @whitneywhtsang)
• #7135 Reduce 2D block read GenISA usage — Shifts more 2D block read operations from the GenISA fallback to the preferred SPIR-V builtin path, improving performance on non-LTS drivers. (+44/-96, @whitneywhtsang)
• #7175 Share 2D block store tile validation — Consolidates duplicate tile parameter validation logic for 2D block store operations, reducing code duplication. (+70/-32, @etiotto)
• #7130 Anchor transpose convert feeding descriptor store — Marks transpose layout conversions feeding descriptor stores as layout anchors, preventing incorrect hoisting that caused wrong results. (+154/-0, @etiotto)
• #7223 Fix pitch < base_width issue when load stride=0 on CRI — Fixes a pitch-vs-base_width ordering bug in 2D block load lowering when the matrix row stride is zero on CRI hardware. (+9/-4, @chengjunlu)
• #7202 Fall back instead of asserting on column_major descriptor load — Replaces a hard assertion in LoadStoreOpToLLVM with a graceful fallback when a column-major descriptor load is encountered. (+3/-7, @dev-tomek)
• #7114 Fix issue in TDESC load/store lowering for reduced rank — Corrects tensor-descriptor load and store lowering when rank reduction is applied, preventing incorrect code generation. (+178/-33, @chengjunlu)
• #7120 Lower math.sin/cos to native HW under TRITON_INTEL_FAST_MATH=1 — Lowers sin and cos to native Intel GPU hardware instructions when fast math is enabled, improving throughput for trigonometric operations. (+138/-2, @etiotto)
• #7029 Replace FP8E4M3FN→FP16 table-lookup converter with single fmul — Replaces the 880-operation software FP8-to-FP16 table lookup with a single hardware fused multiply, resolving the FP8 inference bottleneck identified in #7080. (+196/-67, @etiotto)

Compiler Pipeline & Correctness

Improvements to layout optimization, pass correctness, mask analysis, fast math consolidation, and portability.

• #7220 Add fast-math-gated FP reassociation to open dot-scale hoists — Adds a new reassociation pass that, under fast math, reorders floating-point operations to expose scale-hoisting opportunities in fused attention kernels. (+800/-0, @etiotto)
• #7256 Support sge/sgt/uge/ugt predicates in classifyMask — Extends RemoveMasks to recognize signed and unsigned greater-than/greater-or-equal comparisons as always-true masks, broadening dead-mask elimination. (+244/-18, @whitneywhtsang)
• #7255 Extend getFinalValue to peel through ExtSI/ExtUI — Extends the utility that traces values through control flow to also peel sign-extension and zero-extension ops, enabling better analysis in downstream passes. (+56/-8, @whitneywhtsang)
• #7225 Support offset divisibility check deduced from strides in fused GEMM — Adds logic to verify that offset divisibility constraints for 2D block I/O can be satisfied using stride divisibility information in the fused GEMM pass. (+80/-6, @chengjunlu)
• #7211 Prepare upstreaming for block pointer to tensor descriptor lowering — Refactors the frontend block pointer to tensor descriptor lowering to ease upstreaming to the triton-lang repository. (+23/-18, @whitneywhtsang)
• #7208 Fix global range overflow in Driver — Fixes an integer overflow in the Level Zero driver wrapper when computing global launch dimensions for large grid sizes. (+39/-5, @anmyachev)
• #7147 Make RemoveLayoutConversions cost-aware of 2D block load encodings — Adds a hardware cost model to the layout optimization pass that accounts for 2D block load encoding constraints, preventing layout choices that force expensive fallbacks. (+257/-35, @etiotto)
• #7133 Allow rematerialization of single-use expensive loads in RemoveLayoutConversions — Extends the layout optimization pass to rematerialize expensive loads used by only a single consumer, enabling more layout conversions to be eliminated. (+191/-2, @etiotto)
• #7164 Pre-validate strided pattern in MaterializeBlockPointer — Adds an upfront validation check for strided access patterns in MaterializeBlockPointer, catching invalid configurations before they produce incorrect lowerings. (+13/-15, @etiotto)
• #7165 FuseReshape: Reject fusion when stride divisibility cannot be proven — Prevents FuseReshape from combining operations when the required stride divisibility cannot be statically guaranteed, fixing potential miscompilations. (+50/-0, @whitneywhtsang)
• #7163 Fix RemoveMasks map poisoning on multi-mask ops — Fixes a bug where multiple mask operands on a single operation corrupted the internal mask map, causing incorrect mask removal. (+60/-12, @etiotto)
• #7139 Fix reduce-rank load in Materialize block pointer pass — Corrects handling of rank-reduced tensor loads in MaterializeBlockPointer to avoid incorrect lowering. (+19/-68, @chengjunlu)
• #7123 Fix crash on rank-reducing descriptor loads in OptimizeDotOperands — Prevents a crash when OptimizeDotOperands encounters a descriptor load that reduces the tensor rank. (+35/-4, @whitneywhtsang)
• #7145 Allow CSE pass to optimize sqrt_cr/divide_cr — Marks precise square root and divide operations as eligible for common subexpression elimination. (+19/-4, @anmyachev)
• #7183 Consolidate TRITON_INTEL_FAST_MATH and TORCHINDUCTOR_USE_FAST_MATH — Unifies handling of the two fast-math environment variables to avoid inconsistent behavior depending on which one is set. (+50/-28, @whitneywhtsang)
• #7207 Speed up JIT kernel launch with fast device/stream lookup — Replaces slow Python-wrapped device and stream queries in the XPU JIT launch path with fast C-level lookups, reducing host launch overhead ~1.4x. (+12/-4, @mieshkiwrk)
• #7168 Make load_binary and library linking backend-agnostic for NVIDIA compatibility — Refactors binary loading and library linking so the XPU backend can coexist with NVIDIA's backend in the same Python environment. (+15/-9, @mieshkiwrk)
• #7157 Exclude *.ilk artifacts from wheel — Filters out MSVC incremental linker files from the Windows wheel build, reducing package size. (+16/-2, @anmyachev)
• #7153 Fix portability of 1L << 31 on MSVC — Replaces a non-portable left-shift expression with a standards-compliant equivalent to eliminate MSVC undefined-behavior warnings. (+32/-1, @alona-meir)
• #7137 Fix gluon tests by using GenericLinearEncodingAttr — Updates Gluon dialect lowering tests to use the correct generic linear encoding attribute after an upstream API change. (+4/-60, @anmyachev)

vLLM & Benchmark Infrastructure

Updates to vLLM integration, benchmark additions for SwiGLU and FP8 attention, SYCL-TLA provider infrastructure, and benchmark tooling corrections.

• #6765 Update Triton benchmark attention kernel to SYCL-TLA 0.8 — Migrates the Triton benchmark attention kernel to the SYCL-TLA 0.8 API, aligning it with the current provider interface. (+737/-251, @chengjunlu)
• #7193 Reassociate FP computation to enable hoist in unified attention — Reorders floating-point operations in the vLLM unified attention kernel to expose scale-hoisting opportunities opened by the new reassociation pass. (+18/-1, @quinnlp)
• #7192 Increase BLOCK_M floor to 32 for unified attention kernel — Raises the minimum BLOCK_M tile size in the vLLM unified attention kernel to 32, improving GPU utilization for short-sequence workloads. (+15/-5, @quinnlp)
• #7152 Add fused_gemm_benchmark.py: fused two-GEMM SwiGLU kernel benchmark — Adds a benchmark for a fused two-GEMM SwiGLU activation kernel, providing a representative workload for gated MLP inference. (+247/-0, @app/copilot-swe-agent)
• #7188 Add triton-shim package — Introduces a triton-shim build artifact that allows vLLM to import Triton via a stable shim layer. (+77/-0, @anmyachev)
• #7251 Run all vLLM subsuites from run_vllm_tests — Updates the vLLM test runner to execute all subsuites in a single invocation, improving CI coverage completeness. (+16/-11, @quinnlp)
• #7228 Import vllm tests in benchmarks via sys.path instead of copying — Replaces file-copy based vLLM test imports in benchmarks with sys.path injection, reducing maintenance overhead. (+9/-4, @quinnlp)
• #6998 Add FP8 benchmark path and CI coverage to vLLM fused MoE benchmark — Adds FP8 data type support and CI run coverage to the vLLM fused mixture-of-experts benchmark. (+122/-29, @app/copilot-swe-agent)
• #7187 Use explicit accumulator in tl.dot across benchmarks and tutorials — Updates all benchmark and tutorial kernels to pass an explicit accumulator argument to tl.dot, aligning with the current API and enabling DPAS optimization. (+45/-34, @whitneywhtsang)
• #7105 SYCL-TLA provider for fused MoE benchmark — Adds a SYCL-TLA backend provider for the fused mixture-of-experts benchmark, enabling comparison against the Triton reference. (+44/-21, @dev-tomek)
• #7088 SYCL-TLA provider for unified attention benchmark — Adds a SYCL-TLA backend provider for the unified attention benchmark. (+36/-0, @dev-tomek)
• #7173 Fix incorrect dram_gbps — Corrects the DRAM bandwidth constant used in benchmark efficiency calculations, fixing misleading throughput percentages. (+18/-2, @dev-tomek)
• #7033 Update vllm pin to cf1c906 — Updates the vLLM integration pin and removes tests that now pass after the update. (+181/-401, @quinnlp)
• #7181 Remove three multi-GPU tests from the mamba skiplist — Removes mamba multi-GPU tests from the skiplist after they were confirmed passing on updated hardware. (+62/-9, @sarah12121212)
• #7109 Add install-vllm action that decides how to install vllm-xpu-kernels — Introduces a reusable CI action that selects the correct vLLM installation method based on the runner environment. (+84/-52, @quinnlp)
• #7134 Add mrv2 skips and reorganize mrv2 skiplists — Adds skip entries for known failures on MRv2 hardware and reorganizes the mrv2 skiplist files for clarity. (+40/-43, @quinnlp)
• #7142 Remove XE-TLA residuals — Removes all legacy XE-TLA benchmark code, completing the migration to the SYCL-TLA provider. (+5/-4212, @slawblauciak)
• #6972 Add FP8 input support to flash_attention_benchmark — Extends the flash attention benchmark to accept FP8 input tensors, enabling performance measurement on FP8 attention workloads. (+81/-17, @app/copilot-swe-agent)

Upstream Alignment

6 upstream merges from OpenAI Triton (commits a8419b6, ff8927b, e039939, f5aa532, 94c9863, 20efbd5) — pass rate 99.5%.