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PR Digest Iteration 54
Tiotto, Ettore edited this page Apr 13, 2026
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Period: 2026-03-30 to 2026-04-12 (Iteration 54) | Total PRs: 63 (40 from Xe2/Xe3/Xe3P, 23 from Xe4) | Lines changed: +47,534 / -26,232
The team completed the block pointer removal across the compiler, eliminating over 5,500 lines of legacy code from LoadStoreOp lowering, analysis passes, and RemoveLayoutConversions. New tensor descriptor capabilities were added including PAD_NAN support, rank > 2 lowering, and vectorized gather/scatter. The FpSanitizer and overflow sanitizer passes were enabled for correctness verification. Several RemoveLayoutConversions improvements were ported from upstream. Six upstream synchronizations were completed with pass rates of 97.77%–99.69%.
Key accomplishments:
- Completed the block pointer removal across lowering, analysis, and layout conversion passes, eliminating over 5,500 lines of legacy code
- Expanded 2D block I/O with 1D strided store reshaping, PAD_NAN support, rank > 2 descriptor loads, and vectorized gather/scatter
- Enabled FpSanitizer and overflow sanitizer passes, strengthening correctness verification tooling
- Ported upstream RemoveLayoutConversions improvements (cost gating, copy-on-write semantics), reducing mainline divergence
- Expanded vLLM kernel test coverage on BMG and modernized CI reporting infrastructure
Completing the block-pointer-to-tensor-descriptor migration and expanding 2D block I/O coverage.
- #6549 Remove block pointer handling from LoadStoreOpToLLVM — Removes all block pointer lowering paths from LoadStoreOpToLLVM, completing the migration to tensor descriptor lowering. (+139/-3,477, @whitneywhtsang)
- #6484 Remove TensorDescToBlockPointer — Deletes the TensorDescToBlockPointer fallback pass, now that all paths use native descriptor lowering. (+1/-1,269, @whitneywhtsang)
- #6522 Remove block pointer usage in RemoveLayoutConversion — Eliminates block pointer handling from the layout conversion removal pass. (+126/-595, @whitneywhtsang)
- #6570 Move RewriteTensorPointer to intel — Moves the RewriteTensorPointer pass into the Intel backend to enable Intel-specific customizations. (+650/-18, @whitneywhtsang)
- #6531 Support 1D strided stores via reshape to 2D block IO — Reshapes 1D strided store patterns into 2D tensor shapes eligible for 2D block store lowering. (+608/-11, @etiotto)
- #6504 Enable vectorized gather/scatter for descriptor load/store — Enables vectorized memory operations for descriptor-based loads and stores. (+172/-23, @etiotto)
- #6551 Remove block pointer handling from AxisInfoExt and StrideInfo — Removes block pointer analysis code from AxisInfoExt and StrideInfo. (+6/-164, @whitneywhtsang)
- #6552 Reland partial "Rewrite block pointer to be python-only" — Re-applies the upstream block pointer python-only rewrite with Intel-specific adjustments. (+98/-304, @whitneywhtsang)
- #6548 Support PAD_NAN for tensor descriptor block IO loads — Adds PAD_NAN boundary mode support for out-of-bounds reads in tensor descriptor block loads. (+92/-30, @whitneywhtsang)
- #6418 Support rank > 2 tensors in 2D block I/O lowering — Extends DescriptorLoadOp lowering to handle rank > 2 tensor shapes via batch dimension flattening. (+83/-29, @etiotto)
- #6579 Propagate padding from MakeTensorDescOp to descriptor load/store as attribute — Carries padding information through the descriptor pipeline so downstream passes can use it. (+54/-63, @whitneywhtsang)
- #6538 Pre-apply alignment in descriptor load lowering — Applies 64-byte alignment compensation earlier in descriptor load lowering, simplifying downstream logic. (+62/-0, @whitneywhtsang)
- #6508 Fix descriptor load to respect ttig.one_matrix_per_load attribute — Fixes DescriptorLoadOpToBlockIOConversion to read the one_matrix_per_load attribute instead of hardcoding false. (+30/-1, @whitneywhtsang)
- #6547 Convert fp4tofp.mlir from block pointers to tensor descriptors — Migrates the FP4-to-FP conversion test from block pointers to tensor descriptor syntax. (+26/-33, @whitneywhtsang)
- #6535 Use GenISA for 2D block store 32b_4r4x1c — Falls back to GenISA intrinsics for the unsupported SPIR-V 2D block store configuration 32b_4r4x1c. (+19/-0, @whitneywhtsang)
- #6506 Remove test_block_load references after ae4b45b — Cleans up stale test_block_load references from skip lists after the test was removed. (+11/-19, @whitneywhtsang)
Layout conversion optimizations, sanitizer enablement, upstream porting, and correctness improvements.
- #6469 Enable FpSanitizer pass for Intel XPU backend — Integrates the upstream floating-point sanitizer pass into the Intel compilation pipeline. (+127/-83, @etiotto)
- #6582 Re-enable sanitize-overflow — Re-enables the overflow sanitizer pass after resolving earlier regressions. (+116/-25, @mieshkiwrk)
- #6533 Enable sanitize_overflow — Initial enablement of the overflow sanitizer (later reverted and re-enabled). (+83/-22, @mieshkiwrk)
- #6613 Reduce upstream divergence in DecomposeScaledBlocked — Aligns the Intel DecomposeScaledBlocked pass closer to the upstream implementation. (+62/-35, @etiotto)
- #6621 Replace ballot-based histogram algorithm with atomic-per-element — Switches HistogramOpToLLVM from a ballot-based approach to atomic increments per element, simplifying the lowering. (+48/-107, @etiotto)
- #6574 Port cost gate to hoistConvertOnTopOfExtOrBroadcast — Ports the upstream cost-based gating logic to the Intel layout conversion hoisting pass. (+45/-0, @etiotto)
- #6561 Revert "Enable sanitize overflow" — Temporarily reverts the sanitizer enablement to investigate regressions. (+22/-83, @mieshkiwrk)
- #6573 Port copy-on-write semantics to getRematerializableSlice — Ports upstream copy-on-write rematerialization semantics, preventing unintended IR mutations. (+10/-4, @etiotto)
- #6619 Skip backward propagation when encoding already matches — Adds an early-exit check to avoid unnecessary layout conversion backward propagation. (+7/-0, @etiotto)
- #6580 Replace vector extract with select chain for partitioned shared layout — Switches from vector extract to a select chain for partitioned shared layout lowering, fixing correctness issues. (+6/-9, @wdziurdz)
- #6629 Simplify ext/broadcast loop in hoistConvertOnTopOfExtOrBroadcast — Removes redundant loop structure in the layout conversion hoisting logic. (+2/-21, @etiotto)
6 upstream merges from OpenAI Triton (commits 48a5869, 326fc86, 6cb8445, 851353d, 798d24c, 6786088) — pass rate 97.77%–99.69%.
vLLM test enablement, CI workflow improvements, runtime caching, and developer tooling.
- #6550 Enable tests for P1/P2 vLLM kernels — Enables end-to-end tests for priority vLLM kernels on XPU. (+1,650/-93, @quinnlp)
- #6360 Extract reports into reusable workflow and add manual reports dispatch — Refactors CI reporting into a reusable GitHub Actions workflow. (+318/-64, @vlad-penkin)
- #6515 Update PyTorch pin — Updates the PyTorch dependency pin for CI compatibility. (+59/-2, @anmyachev)
- #6259 Fix tutorials: always collect all FA configs to prevent skiplist missing-test errors on Windows — Ensures all flash attention configurations are collected so skip lists validate correctly. (+38/-11, @app/copilot-swe-agent)
- #6560 Fix skiplist paths after pytest.ini merge from upstream — Corrects skip list file paths broken by the upstream pytest.ini configuration merge. (+16/-29, @exolyr)
- #6568 Skip failing triton-kernels matmul test configurations — Adds known-failing matmul test configurations to the BMG skip list. (+15/-0, @quinnlp)
- #6518 Trim CLAUDE.md and move runtime details to reference doc — Reduces CLAUDE.md size by relocating runtime reference material. (+13/-40, @etiotto)
- #6544 Make test_multi_stream device-agnostic for XPU — Makes the Proton multi-stream test work on XPU devices. (+8/-5, @wdziurdz)
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#6585 Cache results from
get_current_targetcall — Caches the device target query to avoid redundant driver calls at runtime. (+7/-3, @anmyachev) - #6583 Remove merge conflict markers from plugin tests — Cleans up stale merge conflict markers left in plugin test files. (+2/-10, @quinnlp)
- #6630 Remove sed search and replace (cuda -> xpu) commands — Removes unnecessary sed-based cuda-to-xpu string replacements from vLLM scripts. (+1/-8, @quinnlp)
- #6495 Remove TODO regarding GEMM upstream config usage — Removes a stale SYCL-TLA TODO comment now that upstream configs are used. (+1/-11, @mieshkiwrk)