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PR Digest Iteration 55
Tiotto, Ettore edited this page May 1, 2026
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Period: 2026-04-13 to 2026-04-26 (Iteration 55) | Total PRs: 52 (44 from Xe2/Xe3/Xe3P, 8 from Xe4) | Lines changed: +38,706 / -22,524
The team completed the full removal of the legacy block pointer infrastructure — deleting three passes and hundreds of lines of dead code — and landed a wave of new optimizations including elementwise software prefetch, a new HoistLayoutConversions pass, and two new IR cleanup passes to reduce unnecessary conditionals after loop versioning. Several layout conversion correctness fixes landed alongside a significant upstream port that removes the inner tensor type from tensor descriptors. Five upstream synchronizations were completed with a 97.77%–99.74% test pass rate.
Key accomplishments:
- Completed the block pointer to tensor descriptor migration by deleting the BlockPointerToTensorDesc, RewriteTensorPointer, and remaining Intel block pointer passes
- Added elementwise software prefetch for non-dot loads on Xe3P, enabling pipelined memory access in streaming kernels
- Introduced the HoistLayoutConversions pass with a liveness-based GRF budget heuristic to reduce register pressure around layout conversions
- Fixed multiple layout conversion correctness bugs including backward remat conflict detection, dead hoistConvertDotOperand for DPAS, and unsafe hoisting across width-changing ops
- Removed the no-mask restriction from block IO loads, enabling 2D block loads when masks are trivially all-true
Final deletion of legacy block pointer infrastructure and refinements to descriptor-based memory access.
- #6752 Restore non-trivial mask guard for block IO loads — Reinstates the mask guard that prevents 2D block IO on loads with non-trivial runtime masks after the no-mask restriction was removed. (+30/-0, @wdziurdz)
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#6739 Revert 1D strided load → 2D block load reshape — Reverts #6693 due to a batch-16 flex_attention regression caused by an invalid layout for
W < threadsPerWarp. (+29/-549, @whitneywhtsang) -
#6722 Remove inner tensor type inside tensordesc — Ports upstream #9851 removing the inner element type from
TensorDescType, simplifying the type representation. (+1517/-1401, @wdziurdz) - #6721 Remove no-mask restriction from block IO — Allows 2D block IO on loads where the mask is statically all-true, removing a conservative restriction that blocked valid paths. (+79/-9, @whitneywhtsang)
- #6696 Reland "Rewrite block pointer to be python-only" — Completes migration of block pointer rewriting to the Python frontend, eliminating the corresponding C++ pass (fixes #6353). (+97/-625, @whitneywhtsang)
- #6693 Add 1D strided load → 2D block load reshape — Reshapes 1D strided loads into 2D block loads when the access pattern allows it; later reverted in #6739 and relanded with a fix in Iteration 56. (+555/-34, @etiotto)
- #6691 Refactor 1D strided store into reusable helpers — Extracts the 1D strided store reshape logic into standalone utility functions for reuse. (+134/-102, @etiotto)
- #6687 Remove remaining Intel block pointer references — Cleans up residual block pointer code paths after the main migration. (+23/-58, @whitneywhtsang)
- #6686 Fix BMG workflow and move reports to reusable workflow — Fixes the BMG CI workflow and extracts report generation into a shared reusable component. (+11/-68, @whitneywhtsang)
- #6682 Restrict 1D strided store reshape to single row tiles — Prevents incorrect reshape when tile height exceeds one row. (+12/-7, @wdziurdz)
- #6666 Lower block pointers to tensor descriptors in frontend — Adds the Python frontend lowering path from block pointers to tensor descriptor operations. (+74/-9, @whitneywhtsang)
- #6655 Conditionally pre-apply alignment in descriptor load lowering — Applies 64-byte alignment compensation only when the descriptor metadata indicates it is needed. (+46/-13, @whitneywhtsang)
- #6695 Add H==1 test coverage for 1D strided store reshape — Adds test cases for single-row tile edge cases in the strided store path. (+118/-63, @whitneywhtsang)
New passes and kernel-level changes delivering measurable throughput improvements.
- #6712 Elementwise prefetch: software pipelining for non-dot loads (Xe3P+) — Introduces software pipelining for elementwise and streaming loads on Xe3P, overlapping memory latency with compute. (+710/-84, @etiotto)
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#6460 Add HoistLayoutConversions pass with liveness-based GRF budget heuristic — New TTGIR pass that hoists
convert_layoutops earlier in the IR when doing so stays within an 80% GRF budget, reducing live-range pressure near dot operations. (+532/-0, @etiotto) - #6653 Add FoldTrueCmpI and PrepareIfCombining passes — Introduces two new IR cleanup passes that simplify trivially-true comparisons and prepare conditionals for combining, reducing dead branches after loop versioning. (+698/-2, @etiotto)
- #6650 Switch to static launcher — Replaces the dynamic kernel dispatch mechanism with a static launcher for lower per-launch overhead. (+865/-450, @anmyachev)
- #6667 Workaround TIMM reduce accuracy issue — Applies a workaround for incorrect reduction results in TIMM models caused by upstream ReduceOp combine ordering. (+951/-15, @chengjunlu)
- #6497 Workaround TIMM reduce accuracy issue (reland) — Relanded version of #6667 incorporating review fixes. (+954/-15, @whitneywhtsang)
- #6604 Rewrite contiguous descriptor_scatter to descriptor_store — Detects contiguous scatter patterns and converts them into efficient descriptor store ops for 2D block store lowering. (+402/-105, @etiotto)
- #6584 Rewrite contiguous descriptor_gather to 2D block loads — Detects contiguous gather patterns and rewrites them into hardware 2D block load sequences. (+568/-45, @etiotto)
Layout conversion fixes, undefined behavior prevention, and compiler pass improvements.
- #6749 Skip hoistConvertDotOperand across width-changing ops — Prevents layout conversion hoisting across ops that change the K-dimension width, which would produce incorrect dot operand encodings. (+118/-0, @etiotto)
- #6701 Fix backward remat conflict detection — Corrects the conflict detection logic in RemoveLayoutConversions backward rematerialization that could miss conflicting uses and produce invalid IR. (+108/-13, @etiotto)
- #6688 Fix dead hoistConvertDotOperand for DPAS encoding — Removes a dead code path in hoistConvertDotOperand that was never triggered for DPAS encodings, eliminating a potential source of missed hoisting. (+70/-2, @etiotto)
- #6681 Fix dominance violation in hoistConvertOnTopOfExtOrBroadcast — Corrects IR dominance ordering when hoisting layout conversions above extension and broadcast ops. (+88/-13, @wdziurdz)
- #6675 Fix masked div/rem UB exploitation by LLVM O3 — Prevents LLVM O3 from exploiting undefined behavior in masked division and remainder operations that silently produced wrong results. (+120/-93, @etiotto)
- #6730 Implement PredicatedOpInterface on PrefetchOp — Adds predicated op interface to PrefetchOp so it participates correctly in mask-removal and predication lowering passes. (+7/-0, @etiotto)
- #6726 Fix lit test failures due to non-deterministic operation ordering — Stabilizes lit tests that were flaky due to non-deterministic ordering of operations in the output IR. (+10/-10, @whitneywhtsang)
- #6534 Enable tests from test_debug.py — Re-enables previously skipped debug tests and fixes the underlying issues that caused them to fail. (+60/-44, @mieshkiwrk)
5 upstream merges from OpenAI Triton (commits 58816a1, df82d98, 4ddb0bd, 09a2aad, 43badaa) — pass rate 97.77%–99.74%.
vLLM patch cleanup, test unskipping, and framework compatibility improvements.
- #6744 Add Liger Kernels pin — Pins the Liger Kernels dependency version to ensure reproducible CI builds. (+16/-0, @quinnlp)
- #6664 Unskip mrv2 tests — Re-enables previously skipped MRv2 tests that now pass on the current driver. (+32/-16, @quinnlp)
- #6731 Remove skipif_is_rocm from vllm patch — Removes an unnecessary ROCm guard from the vLLM XPU patch that was blocking shared code paths. (+6/-29, @quinnlp)
- #6706 Remove NFC import change from vLLM patch — Removes a non-functional import change from the vLLM patch that was causing merge noise. (+1/-10, @quinnlp)
- #6670 Remove malformed section in vLLM patch — Cleans up an invalid patch section that caused application warnings during vLLM installation. (+19/-64, @quinnlp)
- #6467 Remove cuda→xpu replacements from vllm-fix.patch — Eliminates CUDA-to-XPU string replacements now handled natively by vLLM upstream. (+2/-127, @quinnlp)
- #6617 Move vLLM benchmarks to triton_kernels_benchmark package — Consolidates vLLM benchmarks into the shared benchmark infrastructure. (+29/-29, @quinnlp)
- #6601 Add vllm-tests BMG workflow — Creates a dedicated CI workflow for running vLLM tests on BMG hardware. (+15/-0, @quinnlp)
Benchmark additions, CI infrastructure improvements, and skiplist maintenance.
- #6476 Update benchmark CI to install from pre-built wheel artifact — Switches benchmark CI to use a pre-built wheel artifact rather than building from source, reducing CI setup time. (+231/-23, @januszjah)
- #6716 Skip failing mamba tests — Adds mamba tests to the skip list pending investigation of #6713. (+10/-0, @quinnlp)
- #6703 Fix stale swiglu_opts indices in xe2 triton_kernels skiplist — Updates shifted parametrize indices after upstream added a new test case. (+10/-10, @exolyr)
- #6679 Loosen CPU RAM check in gemm_postop_addmatrix int8 benchmark — Relaxes the memory threshold to allow the benchmark to run on systems with less RAM. (+6/-4, @whitneywhtsang)
- #6610 Add fused MoE to benchmark — Adds a fused mixture-of-experts kernel to the benchmark suite. (+489/-0, @chengjunlu)
- #6599 Update PyTorch pin — Updates PyTorch dependency version for CI stability. (+3/-58, @anmyachev)