PR Digest Iteration 58

PR Summary

Period: 2026-05-24 to 2026-06-06 (Iteration 58) | Total PRs: 56 (47 from Xe2/Xe3/Xe3P, 9 from Xe4) | Lines changed: +62,873 / -12,195

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Triton XPU BE (Xe2/Xe3/Xe3P) (47 PRs, +7,482 / -1,351)

The sprint delivered significant work across the compiler, runtime, and integration stacks. FP8 conversion performance was improved on multiple paths, replacing software table-lookup converters with single hardware multiply instructions. New SPIR-V builtins for sigmoid and native sin/cos were added to the Intel libdevice, and predicated load was enabled by default for tensor-of-pointers access. The Proton profiling backend was relanded for XPU, and a pointer-vector scalarization pass was added to fix SPIR-V translation correctness. Two upstream synchronizations were completed with a 99.06% test pass rate.

Key accomplishments:

• Replaced FP8 table-lookup converters with hardware fused multiplies across three FP8 types, substantially reducing FP8 conversion overhead
• Enabled sigmoid SPIR-V builtins and added fast sin/cos to Intel libdevice, expanding native hardware instruction coverage
• Relanded the Proton XPU profiling backend, restoring performance profiling capability
• Added EVICT_LAST cache promotion for known-reuse dot-fed loads, improving L1 hit rates on matrix workloads
• Maintained upstream alignment with a 99.06% pass rate across two synchronizations

Memory Access & Lowering

Lowering improvements for 2D block I/O, pointer-vector scalarization, predicated loads, prefetch placement, and hardware surface-pitch safety.

• #7066 Enable TRITON_INTEL_PREDICATED_LOAD for tensor of pointers load by default — Enables predicated scalar load lowering by default for tensor-of-pointers access patterns, improving performance on non-contiguous pointer tensors. (+12/-7, @whitneywhtsang)
• #7052 Add ScalarizePtrVectorsPass to remove pointer vectors before SPIR-V — Adds a new LLVM IR pass that scalarizes pointer vector types before SPIR-V translation, fixing correctness issues with pointer aggregates. (+182/-4, @wdziurdz)
• #7044 Skip 1D->2D reshape when block IO for all layouts is disabled — Prevents MaterializeBlockPointer from applying a 1D-to-2D reshape optimization when 2D block I/O is globally disabled, avoiding unnecessary IR transforms. (+95/-0, @etiotto)
• #7036 Skip block IO when surface pitch exceeds 24-bit hardware limit — Supersedes #7032 with a second variant of the 24-bit surface pitch guard applied earlier in the lowering pipeline. (+98/-4, @dev-tomek)
• #7032 Skip block IO when surface pitch exceeds 24-bit hardware limit — Returns null pitch when the computed surface pitch exceeds the 24-bit hardware limit, gracefully falling back to vectorized loads and preventing a verifier crash on real PyTorch workloads such as T5. (+119/-2, @dev-tomek)
• #7018 Use upstream loop.stage/loop.cluster annotations to drive XPU prefetch op placement — Wires the Intel prefetch pass to consume the upstream loop.stage and loop.cluster IR annotations, aligning XPU prefetch scheduling with the upstream software-pipelining framework. (+306/-9, @etiotto)

Compiler Pipeline & Correctness

FP8 converter rewrites, new SPIR-V builtins, libdevice extensions, cache promotion, and compile-time crash fixes.

• #7079 Gate FP8E4M3FN->BF16 fmul converter on bf16 arithmetic support — Guards the FP8E4M3FN-to-BF16 fmul converter behind a capability check so it is only emitted on hardware that supports BF16 arithmetic. (+146/-8, @etiotto)
• #7064 Add fast_sinf and fast_cosf to Intel libdevice — Adds hardware-accelerated fast sine and cosine implementations to the Intel libdevice library, enabling native sin/cos lowering under fast math. (+110/-0, @etiotto)
• #7059 Support ttg.local_atomic_scatter_rmw lowering for Gluon — Adds lowering support for the ttg.local_atomic_scatter_rmw Gluon dialect op, enabling atomic scatter operations through shared memory. (+228/-38, @mieshkiwrk)
• #7050 Replace FP8E5M2->BF16 table-lookup with mask-free fmul rebias — Replaces the FP8E5M2-to-BF16 software table lookup with a mask-free fused multiply rebias, eliminating the table and reducing conversion cost. (+256/-4, @etiotto)
• #7040 Replace FP8E4M3FN->BF16 table-lookup with single fmul rebias — Replaces the FP8E4M3FN-to-BF16 software table lookup with a single hardware fused multiply rebias. (+181/-74, @etiotto)
• #7070 Enable sigmoid SPIR-V builtins — Lowers sigmoid operations to the SPV_INTEL_sigmoid SPIR-V extension builtin when available, replacing the software approximation. (+151/-1, @anmyachev)
• #6978 EVICT_LAST promotion for known-reuse dot-fed loads — Extends the AnnotateCacheControl pass to promote dot-operand loads with proven reuse to EVICT_LAST cache policy, improving L1 cache retention for matrix operands. (+478/-66, @etiotto)
• #7020 Add TritonGen Op SubGroupBitcastShuffle — Adds a TritonGEN op that fuses a bitcast with a sub-group shuffle, enabling cheaper lane-level data movement in layout conversion lowering. (+100/-6, @chengjunlu)
• #7065 Fix #5665: use perf_counter_ns for compile timing — Replaces deprecated timing calls with perf_counter_ns to fix compilation time measurement accuracy, resolving #5665. (+13/-9, @ksmoliansky)
• #7011 Split cleanup phase; tolerate SCF non-convergence — Ports upstream PR #10132 to split ConvertLayoutOp canonicalization (must converge) from scf canonicalization (best-effort), preventing compilation crashes on deeply-unrolled scf.if ladders in vLLM kernels. (+14/-6, @etiotto)
• #6991 Revert tt.local_alloc for i1 type change — Reverts an earlier i1 tt.local_alloc change after upstream confirmed the configuration is invalid. (+11/-116, @chengjunlu)
• #6985 Extend ReuseAnalysis with knownReuse helper — Adds a knownReuse(load) helper that returns true only when at least one underlying analysis positively proves reuse, giving aggressive optimizations a safer signal than the previous best-guess query. (+140/-0, @etiotto)
• #6999 Fix MLIR TypeID crash in AnnotateCacheControl for AliasInfo — Fixes a crash caused by an MLIR TypeID collision in the AliasInfo data structure used by the AnnotateCacheControl pass. (+1/-4, @mieshkiwrk)

Proton & Runtime

Proton XPU profiling backend restoration and Gluon/SPIR-V interface extensions.

• #7049 Reland proton backend registration for XPU — Relands the Proton performance profiling backend registration for the XPU target after resolving issues that required the initial revert. (+656/-84, @wdziurdz)
• #7116 Add new invalid SPV interfaces to TritonGen — Registers additional SPIR-V interface signatures as invalid in the TritonGEN dialect to guide GenISA fallback selection. (+25/-0, @whitneywhtsang)
• #7115 Add new invalid SPV interfaces to TritonGen — Additional invalid SPV interface registrations. (+15/-0, @chengjunlu)
• #7113 Add new invalid SPV interfaces to TritonGen — Additional invalid SPV interface registrations. (+10/-0, @chengjunlu)
• #7082 Add blockptr-to-tdesc skill — Adds a Claude Code skill for migrating Triton kernels from the deprecated block-pointer API to the modern tensor-descriptor API. (+1223/-0, @etiotto)

Upstream Alignment

2 upstream merges from OpenAI Triton (commits ac7445b, 2c873e5) — pass rate 99.06%.

• #6997 Sync third_party/amd files with upstream c7391a2 — Removes stale merge-conflict residue from three third_party/amd files that upstream had already deleted at commit c7391a2. (+1/-20, @etiotto)

vLLM & Benchmark Infrastructure

vLLM XPU kernel source build, BMG support, SYCL-TLA benchmark migration, and Python 3.15 readiness.

• #6926 Build vLLM XPU kernels from source and upload via nightly wheels — Adds CI infrastructure to build vLLM XPU kernels from source and distribute them via the nightly wheel pipeline. (+402/-214, @quinnlp)
• #6846 Add BMG versions of vLLM skiplists and BMG-specific skips — Adds separate vLLM skip files for BMG hardware and fills in BMG-specific attention test skips. (+557/-0, @quinnlp)
• #7132 Skip w8a8_fp8_fused_moe tests with accuracy errors on PVC — Adds skip entries for w8a8 FP8 fused MoE tests that produce accuracy failures on PVC pending investigation. (+28/-0, @quinnlp)
• #6883 Add SYCL-TLA Split-K GEMM benchmark — Adds a Split-K GEMM benchmark using the SYCL-TLA provider. (+220/-24, @slawblauciak)
• #6879 Replace XE-TLA with SYCL-TLA in generic GEMM and OneDNN benchmark — Migrates the generic GEMM and OneDNN benchmark from the deprecated XE-TLA provider to SYCL-TLA. (+11/-15, @slawblauciak)
• #6882 Remove XE-TLA references from fused_softmax benchmark — Removes legacy XE-TLA references from the fused softmax benchmark. (+4/-14, @slawblauciak)
• #7111 Add Python 3.15 to nightly wheel builds — Adds Python 3.15 to the matrix of Python versions built in the nightly wheel workflow. (+8/-3, @whitneywhtsang)
• #7057 CRI fallback to CPU when SYCL kernel issues occur — Adds a CPU fallback in CRI test paths when SYCL kernel issues are detected, preventing test suite hangs. (+9/-6, @chengjunlu)
• #7038 Sync E2E model list from torch-xpu-ops — Updates the end-to-end model test list to match the current torch-xpu-ops model coverage. (+11/-0, @anmyachev)
• #7031 Add dynamic input size adjustment for CRI — Adjusts default benchmark input sizes dynamically when running on CRI hardware. (+10/-6, @whitneywhtsang)
• #7019 Fix spirv-dis build for PredicatedIOINTEL support — Builds spirv-dis from a pinned source commit so the SPV_INTEL_predicated_io capability decodes correctly under DLE 2026.0. (+1/-12, @whitneywhtsang)
• #7015 Add dynamic input size adjustment in tutorials for CRI — Adds is_xpu_cri() detection to tutorials 03/03a/05/09 to shrink inputs automatically on CRI hardware. (+43/-15, @whitneywhtsang)
• #7014 Fix CI issues on release branch for DLE2026 — Cherry-picks release-branch CI fixes to simplify the switch to oneAPI 2026.0. (+4/-67, @anmyachev)
• #7012 Use -cl-fp32-correctly-rounded-divide-sqrt for LTS (cherry-pick) — Cherry-picks the IEEE-correct fp32 divide/sqrt build flag onto the release branch for LTS drivers. (+55/-1, @anmyachev)
• #7010 Update vLLM XPU translator script and mamba skiplist — Teaches the vLLM XPU translator to rewrite .cuda() to .xpu() and removes a mamba test from the skip list after it began passing. (+14/-1, @sarah12121212)
• #7008 Fix failing test_selective_state_update in test_mamba_ssm — Reorders the PyTorch reference computation in the mamba SSM test to match the kernel's bf16 rounding sequence, fixing a spurious mismatch. (+19/-2, @sarah12121212)
• #7006 Use -cl-fp32-correctly-rounded-divide-sqrt for LTS — Adds the IEEE-correct fp32 divide/sqrt build flag for the LTS driver path. (+55/-1, @anmyachev)
• #6995 Add NVL archs — Adds NVL architecture definitions so subsequent CI and test paths can target NVL hardware. (+11/-0, @anmyachev)
• #6990 Workaround for unified attention BMG OOM failures — Adds a temporary workaround skip for unified-attention OOM failures on BMG, tracking #6759 for a permanent fix. (+11/-0, @dev-tomek)
• #6954 Fix test_device_assert_barrier crash on BMG with --forked — Converts test_device_assert_barrier to subprocess isolation so xdist and pytest-forked don't inherit corrupted Level Zero state on BMG, fixing #6819. (+29/-11, @januszjah)
• #6924 Add inductor cooperative-reductions test and align Windows test suite — Adds the inductor cooperative-reductions test and brings the Windows test suite into alignment with the Linux configuration. (+36/-42, @anmyachev)