Firtool 1.59.0 Release

What's Changed

• [Debug] Honor dbg dialect ops in DebugInfo analysis by @fabianschuiki in #6310
• [ESI] Service requests now track AppIDs rather than instance hierarchy by @teqdruid in #6328
• [FIRRTL] Add debug info materialization pass by @fabianschuiki in #6309
• [firtool] Move -g option into firtool library by @fabianschuiki in #6332
• [ESI][Services] Leave breadcrumbs while connecting services by @teqdruid in #6331
• Rename sel on calyx.mux to cond by @rachitnigam in #6333
• [ESI] Add HasAppID op interface by @teqdruid in #6337
• [FIRRTL][LowerTypes] Keep the order of bundle fields in lowered cat by @SpriteOvO in #6339
• Disable MLIR install of CIRCT projects by @GeorgeLyon in #6340
• [ESI] Build AppID hierarchy for building manifest by @teqdruid in #6338
• [FIRRTL] Add a new pass to detect static asserts by @prithayan in #6341
• [FIRRTL] Add bool isFlip argument to walkGroundTypes callback by @prithayan in #6344
• [ESI] Add AppID design hierarchy manifest data to the manifest by @teqdruid in #6345
• Bump LLVM to 7ce613fc77af092dd6e9db71ce3747b75bc5616e by @fabianschuiki in #6342
• [Debug] Add debug-only value/op analysis by @fabianschuiki in #6335
• [ESI] Include designer-specified and service info in manifest by @teqdruid in #6346
• [CMake] Re-add install targets for CIRCT libraries by @GeorgeLyon in #6347
• [CI] Don't include deleted Python files in yapf check by @teqdruid in #6350
• [ESI] Rip out Cap'nProto schema generation by @teqdruid in #6349
• [OM] Convert list create ops for lists of paths in FreezePaths. by @mikeurbach in #6336
• [CAPI][MSFT]: Remove include of C++ header in C-API by @devins2518 in #6353
• [ESI] Move Cap'nProto into ESI runtime by @teqdruid in #6354
• [ESI] Not every build has zlib by @teqdruid in #6356
• [Ibis] Mark all not-illegal ops as legal by @teqdruid in #6355
• [OM] Add Python bindings for path types. by @mikeurbach in #6361
• [ESI][Cosim] DPI support for manifests by @teqdruid in #6357
• [ESI] Compressed manifest lowering for cosim by @teqdruid in #6358
• [Arc] Align >=128-bit integers to 16 bytes by @maerhart in #6366
• [Arc] Support lowering of seq clock type and conversion operations by @maerhart in #6367
• [Ibis] Refactor to use inner symbols by @mortbopet in #6369
• [ExportVerilog] Support parameterized length unpacked arrays by @teqdruid in #6362
• [CombToArith] Explicitly handle wide shifts to avoid UB by @fzi-hielscher in #6352
• [HW] Reference struct/union fields by index by @fzi-hielscher in #6266
• [HW] Resolve parametric types in the InstanceOp builder by @teqdruid in #6364
• [ESI] Major cosim fixup/cleanup/update by @teqdruid in #6365
• [ESI] Cosim integration test without runtime by @teqdruid in #6370
• [Arc] Remove hw.wire once it is tapped by @maerhart in #6372
• [ESI] Basic Python runtime for manifests by @teqdruid in #6371
• Bump LLVM to 3026c1361294a6d20c0d7dd5a3947b2c793873de by @fabianschuiki in #6375
• [Comb] Update Python binding decorators to wrap in the right order. by @mikeurbach in #6377

New Contributors

• @devins2518 made their first contribution in #6353

Full Changelog: firtool-1.58.0...firtool-1.59.0

Firtool 1.58.0 Release

What's Changed

• [MSFT] Add multicycle path op by @mortbopet in #6262
• [PyCDE] Support ESI bundles by @teqdruid in #6288
• [ESI] Start of system manifest: types by @teqdruid in #6290
• Remove old workflow by @GeorgeLyon in #6306
• [Debug] Include Verilog instance names in HGLDD output by @fabianschuiki in #6299
• [ESI] Rip out C++ API generator for cosim by @teqdruid in #6300
• [ESI] Ditching service metadata by @teqdruid in #6301
• [ESI][NFC] Misc improvements for bundle ops by @teqdruid in #6312
• [MergeConnections] Handle type alias by @uenoku in #6314
• [ESI] Move services over to bundles by @teqdruid in #6302
• firtoolPopulateCHIRRTLToLowFIRRTL doesn't need a module by @GeorgeLyon in #6304
• [LowerToHW] Avoid uninit plusargs.value reg by @seldridge in #6313
• [ExportVerilog] Fix struct inject op emisson by @uenoku in #6325
• [Debug] Add debug dialect by @fabianschuiki in #6308
• LLVM Bump by @debs-sifive in #6322
• [OM] Add evaluator support for paths by @youngar in #6320
• [ESI] Fix operation deletion in services connecting by @teqdruid in #6323
• [FIRRTL] Update ExtractInstances to use the new instance symbol. by @mikeurbach in #6327
• [FIRRTL] LowerAnnotations: Allow annotationRecords to be extended externally by @uenoku in #6296

Full Changelog: firtool-1.57.1...firtool-1.58.0

Firtool 1.57.1 Release

What's Changed

• Fix performance regression in verifiers by @darthscsi in #6293

Full Changelog: firtool-1.57.0...firtool-1.57.1

Firtool 1.57.0 Release

What's Changed

• [FIRRTL][HoistPassthrough] Add pass to hoist must-driven output ports. by @dtzSiFive in #6115
• Remove GlobalRefOp, GlobalRefAttr by @seldridge in #6173
• [FIRRTL][DropConst] Mark InstanceGraph preserved. by @dtzSiFive in #6183
• [firtool] Add LowerGroups pass by @seldridge in #6182
• [FIRRTL][Hoist] Mark all analyses preserved if no changes. by @dtzSiFive in #6185
• [firtool] Deprecate -dedup option by @seldridge in #6188
• [Ibis] Allow tunneling from hw.modules by @mortbopet in #6195
• [Pipeline] Remove internal clock, reset,stall signals. by @mortbopet in #6196
• [Ibis] Print offending port name and use count on containers-to-hw error by @blakep-msft in #6186
• [FIRRTL][LOA] If no changes made, mark all analyses preserved. by @dtzSiFive in #6187
• [Ibis] Fix clean selfdrivers in case of external reads by @mortbopet in #6201
• [ExportVerilog] Format specifiers: hierpath separation character by @teqdruid in #6192
• [FIRRTL] Add GroupSink pass by @seldridge in #6184
• [FIRRTL] Cause "weak" OMIR Annotations to not block optimizations by @seldridge in #6200
• [Ibis] Fix issues in Tunneling and PortRef lowering by @mortbopet in #6202
• [Python] Use Ninja and LLD when building wheel if available by @uenoku in #6165
• [FIRRTL][RefSubOp] Add getAccessedField helper method. by @dtzSiFive in #6208
• [OM][Bindings] Make Python Evaluator Object hashable by @prithayan in #6204
• [ExportVerilog] Fix line count in debug verilog locations by @prithayan in #6210
• [FIRRTL] Simplify getFieldRefFromValue, add+use FieldRefCache. by @dtzSiFive in #6181
• Bump LLVM by @rwy7 in #6207
• llvm: Small bump to get version that passes tests. by @dtzSiFive in #6211
• [Seq][FirMemLowering] Create correct width constant for missing mask input by @prithayan in #6214
• [Ibis] Add ibistool by @mortbopet in #6206
• [Ibis] Reblock should also create blocks around non-delimited ops by @mortbopet in #6218
• [Ibis] Add ibis-prepare-scheduling pass by @mortbopet in #6166
• [FIRRTL][LOA][NFCI] Use FieldRefCache. by @dtzSiFive in #6215
• [FIRRTL] Bump FIRRTL version to 3.3.0 for parsing by @seldridge in #6217
• [Arc] Move LegalizeStateUpdate before StateAlloc by @zyedidia in #5830
• [HW] Change printer for modules by @darthscsi in #6205
• [MSFT] Remove Python extensions for non-existant structure ops. by @mikeurbach in #6221
• [ibis] Fix reblock use of erased ops by @seldridge in #6222
• [FIRRTL][Parser] Update groups version check to 3.2.0. by @dtzSiFive in #6219
• [Calyx] Add calyx.undef by @rachitnigam in #5964
• [HW] Disallow duplicate field names in HW aggregate types by @fzi-hielscher in #6225
• [Firtool][CAPI] Add C-API for Firtool lib by @SpriteOvO in #6036
• [Ibis] Add ibis.sblock.isolated by @mortbopet in #6230
• [OM] Implement PathAttr CAPI and Python binding by @uenoku in #6229
• [Ibis] Add handshake to DC conversion by @mortbopet in #6231
• [FIRRTL] Preserve port orders when lowering to HW. by @darthscsi in #6224
• [FIRRTL] Input probe support. by @dtzSiFive in #6121
• [ExportVerilog] Bound type size considered for decl alignment by @fabianschuiki in #6171
• [FirRegLowering] Implement refined check for mux-to-if conversion. by @mikeurbach in #6203
• [ESI] Lower bundles to channels by @teqdruid in #6216
• [Ibis] Add methods-to-containers pass by @mortbopet in #6232
• [Firtool] Rerun IMCP after register optimizations by @uenoku in #6179
• [FIRRTL][ExpandWhens] Support flow checking for local and remote objects by @rwy7 in #6212
• [Ibis] Added missing ibistool to integration test by @dobios in #6241
• [OM] Load post-export dialects in om-linker. by @mikeurbach in #6242
• [FIRRTL] Update LowerClasses to use the defname for ExtModules. by @mikeurbach in #6243
• [Arc] Add LowerArcsToFuncs pass by @zyedidia in #6227
• [ESI][Python] Expose BundleType to Python by @teqdruid in #6248
• [FIRRTL] Add canonicalizations for mux comparing its high and low operands by @trilorez in #6246
• [FIRRTLFolds] Remove InvalidValue canonicalization by @uenoku in #6080
• [Ibis] Add scheduling prototype by @mortbopet in #6239
• [Arc] Lower models into eval functions by @fabianschuiki in #6247
• [OM] Update FreezePaths to root paths at the nearest public module. by @mikeurbach in #6244
• [Debug] Add basic DebugInfo analysis and emission by @fabianschuiki in #6148
• [PyCDE] Fixing tests by @teqdruid in #6252
• [OM] Add more path types by @youngar in #6250
• [OM] Evaluator: Support graph regions by @uenoku in #6249
• [SV] Mark sv.xmr.ref op as pure by @fabianschuiki in #6260
• [FIRRTL][FIRParser] Prefer RWProbe op as much as possible. by @dtzSiFive in #5835
• [FIRRTL][MergeConnections] Reject non-passive aggregates. by @dtzSiFive in #6264
• [FIRRTL][NFC] Move FieldRef -> InnerSymTarget to utility. by @dtzSiFive in #6265
• [Seq] Add optional power-on value to compreg ops by @mortbopet in #6255
• [Seq][NFC] More flexible builders for compregs by @nandor in #6270
• [firtool] Add infra for pass plugins by @uenoku in #6254
• [Seq] Remove custom printer/parser for seq.compreg(.ce) ops by @mortbopet in #6267
• [PipelineToHW] Add optional power-on values to control registers by @mortbopet in #6269
• [Seq] Fix the canonicalization of seq registers with a clock type by @nandor in #6274
• [OM] Add location info to EvaluatorValue by @prithayan in #6240
• [FIRRTL][GrandCentral] Add a mode to drop companion modules by @nandor in #6268
• [circt-opt] Export symbols for MLIR plugins by @uenoku in #6278
• [CI] Install LLVM utils to release artifacts by @uenoku in #6279
• [OM] Overhaul of path operations by @youngar in #6253
• [Namespace] Return an empty string for empty string. by @uenoku in #6284
• [NFC] LLVM Bump by @trilorez in #6280
• [FIRRTL] Add strip option to DropName by @uenoku in #6281
• [LowerToHW] Fix symbol creation for empty names by @uenoku in #6282
• [ExtractTestCode] Specify non-empty unqiue port names by @prithayan in #6283
• Add emission for calyx std_signext by @rachitnigam in #6285
• [FIRRTL] Remove RecursiveMemoryEffects and RecursivelySpeculatable from When op, add canonicalizers by @uenoku in #6236
• [HW] round trip ModuleType non-ssa values by @darthscsi in #6287

New Contributors

• @dobios made their first contribution in #6241

Full Changelog: firtool-1.56.1...firtool-1.57.0

Firtool 1.56.1 Release

What's Changed

• [MSFT] Finally move away from GlobalRefOp by @teqdruid in #6168
• [FIRRTL] Add Double property type. by @dtzSiFive in #6167
• [MSFT] Rip out MSFTModule et. al. by @teqdruid in #6161
• [HW] Allow for quoted struct field names by @fabianschuiki in #6174
• [MSFT] Remove DiscoverAppIDs pass by @teqdruid in #6175
• [Python] Remove CI options that only applied to MacOS universal. by @mikeurbach in #6169
• [NFC][ESI][MSFT] Move AppIDs over to ESI by @teqdruid in #6177
• [Ibis] Add Ibis CF to Handshake conversion by @mortbopet in #6164
• [Python] Downgrade setuptools_scm, drop python 3.7 as EOL by @uenoku in #6180

Full Changelog: firtool-1.56.0...firtool-1.56.1

Firtool 1.56.0 Release

What's Changed

• [Pipeline] Add non-stallable pipeline stages by @mortbopet in #6018
• [OM] Handle AnyType casts in Evaluator. by @mikeurbach in #6106
• [OM][firtool] Add FreezePaths pass by @youngar in #6069
• [CI] Use macOS universal wheels for M-series, add Python 3.9 and 3.11 support by @leonardt in #5822
• Add OMInstanceTarget path kind by @youngar in #6123
• [Arc] Introduce vectorize operation by @maerhart in #6120
• [Pipeline] Fix issue in ExplicitRegs by @mortbopet in #6118
• [Ibis] Add ibis reblock pass by @mortbopet in #6089
• [HW] Support parametric UnpackedArrayType in hw-specialize by @mortbopet in #6119
• [Ibis] Rename ibis.block -> ibis.sblock by @mortbopet in #6125
• [FIRRTL][IMCP] Fix handling of refsub, send/resolve, fields. by @dtzSiFive in #6100
• [FIRRTL][Parser] Wires of non-agg non-hw should have droppable names. by @dtzSiFive in #6102
• [FIRRTL][Inliner] Use wires for all. by @dtzSiFive in #6127
• [FIRRTL][LowerClasses] Handle InstanceTarget. by @dtzSiFive in #6126
• [PyCDE] Move off of msft.module to hw.module by @teqdruid in #6122
• [OM] Add path append op by @prithayan in #6073
• [HW] Unify port location arrays and port attribute arrays by @darthscsi in #6116
• [FIRRTL][Dedup] An extmodule without defname is unique. by @dtzSiFive in #6129
• [FIRRTL][Dedup] Skip modules with syms we can't drop, classes. by @dtzSiFive in #6133
• [Arc] Include pass base only where needed by @maerhart in #6140
• [Arc] Improve performance of state update legalization by @fabianschuiki in #6137
• [Arc] Add LowerVectorizations pass by @maerhart in #6141
• [Arc] Allow top-level logic in LowerState; detect clock edges by @fabianschuiki in #6142
• [Handshake] Allow handshake ops to be used outside of a handshake.func by @mortbopet in #6132
• [Seq] Convert seq.clock_gate to use the clock type exclusively by @nandor in #6134
• [Seq] Switch all seq ops to use seq.clock by @nandor in #6139
• [Seq] Lower clock types nested within aggregates by @nandor in #6138
• [FIRRTL][FIRParser] Add AnyRef cast as-needed for agg prop expr's. by @dtzSiFive in #6135
• [scf-to-calyx]Support for function call by @linuxlonelyeagle in #5965
• [Firtool] Move the remaining pass additions into lib by @SpriteOvO in #6094
• [Ibis] Add ibis.sblock inlining operations and passes by @mortbopet in #6145
• [HW][Python] Add name getters for ModuleType by @uenoku in #6149
• [OM] Python bindings for om integer by @prithayan in #6042
• [Ibis] Allow multiple return values for ibis.method by @mortbopet in #6151
• [NFC][Handshake] Adjust handshake interface defs and file locs by @mortbopet in #6150
• [ExportVerilog] Support CallSiteLoc and NameLoc emission by @mortbopet in #6131
• [ExportVerilog] Add verilog debug locations to output MLIR by @prithayan in #6092
• [FIRRTL][IMDCE] Mark all objects as alive by @rwy7 in #6157
• [ExportVerilog] Remove useless assert from NameCollector by @fabianschuiki in #6147
• [CI] Hotfix macosx python wheel by @leonardt in #6158
• [MSFT] Make AppID discovery an index rather than a pass by @teqdruid in #6152
• [PyCDE] Switch over to new AppIDIndex by @teqdruid in #6160
• [HW] Align instance_like_impl verification with getReferencedModule by @mortbopet in #6155
• [NFC][ExportVerilog] Move location emission functions to class by @mortbopet in #6154
• [CFToHandshake] Refactor towards genericness by @mortbopet in #6156
• [Ibis] Add ibis.method.df operation by @mortbopet in #6163
• [HW] Fix ModuleType::getInputType to return InOutType for InOut port by @uenoku in #6162

New Contributors

• @leonardt made their first contribution in #5822

Full Changelog: firtool-1.55.0...firtool-1.56.0

Firtool Release 1.55.0

What's Changed

• [FIRRTL] Update LowerClasses to handle extmodule and instances. by @mikeurbach in #6063
• [FIRRTL] Improve IMCP for non-hw; support mat'izing refs of constants. by @dtzSiFive in #6091
• [FIRRTL][IMDCE] Don't try to remove main module, don't warn if empty. by @dtzSiFive in #6065
• [SFCCompat] Regard aggregate constant as constants by @uenoku in #6083
• [Ibis] Introduce ibis.block instead of ibis.schedule by @mortbopet in #6082
• [Ibis] Add --ibis-argify-blocks pass by @mortbopet in #6084
• [FIRRTL][IMCP] Names of wires of probes can be deleted. by @dtzSiFive in #6097
• [FIRRTL][IMCP] Propagate through nodes with annotations, but keep. by @dtzSiFive in #6098
• [FIRRTL][LOA] Created Non-HW wires should always have droppable names. by @dtzSiFive in #6101
• [FIRRTL][IMDCE] Wires for all (probes). by @dtzSiFive in #6056
• [OM] Add AnyType and AnyType cast. by @mikeurbach in #6105
• [FIRRTL] Add AnyRef type, parser, emitter, and printed form. by @mikeurbach in #6104
• [HW] Convert type storage for modules over to moduletype by @darthscsi in #6071
• [MSFT] Remove the partition pass by @teqdruid in #6110
• [ESI] Channel bundle type and pack/unpack ops by @teqdruid in #6066
• [Pipeline] Remove outlined lowering by @mortbopet in #6111
• [OM] Evaluator: Support Map by @uenoku in #6045
• [FIRRTLFolds] Make sure single connection is in the same block by @uenoku in #6085
• Remove arg and res names from module representation by @darthscsi in #6095
• [FIRRTL] Optionally look through casts for fieldref chasing. by @dtzSiFive in #6093
• Bump LLVM: 2023/09/12 by @azidar in #6114
• [FIRRTLFolds] Ignore reset signals for constant registers in foldHidd… by @uenoku in #6113
• [FIRRTL] Add AnyRef cast operation, and insert during parsing. by @mikeurbach in #6108
• [FIRRTL] Update LowerClasses to handle AnyRef and AnyRef cast. by @mikeurbach in #6117
• [SV] Add optional init operand to sv.reg by @mortbopet in #6002

Full Changelog: firtool-1.54.0...firtool-1.55.0

firtool-1.54.0

What's Changed

• [NFC] rename function and move interface to a file by @darthscsi in #6021
• [FIRRTL][IMCP] Test and don't error on object/object.subfield. by @dtzSiFive in #6022
• [FIRRTL] Bump latest to 3.2.0 for use in emitter / round-trip. by @dtzSiFive in #6026
• [FIRRTL] Adjust bool version guard to accurate 3.2.0. by @dtzSiFive in #6027
• [FIRRTL] Add Path + List ops to visitor/emitter by @dtzSiFive in #5959
• [ESI][Cosim] Reducing MMIO data widths to 32 bit by @teqdruid in #6017
• [ESI] Start of new software runtime by @teqdruid in #5999
• [HW] Fold extracts of constant structs by @fzi-hielscher in #6010
• [FIRRTL] Add an ExtClassOp by @rwy7 in #5954
• [OM] Add integer type by @prithayan in #6030
• [OM][LowerClass] Lower firrtl.integer to om.integer by @prithayan in #6031
• [FIRRTL] Implement InstanceGraphInstanceOpInterface for ObjectOp by @rwy7 in #6041
• [FIRRTL] Gate classes behind firrtl version 3.2.0 by @rwy7 in #6043
• [Verif][LTL] Add basic python binding support by @uenoku in #6040
• [FIRRTL] Parse and lower Open Aggregates Wires by @seldridge in #6028
• [SV] Fix --hw-eliminate-inout-ports by @mortbopet in #6037
• [circt-lec] Generalise LEC to handle non-SSA modules by @TaoBi22 in #5319
• [FIRRTL][IMCP] Don't delete wire if only force result is used. by @dtzSiFive in #6058
• [Seq] Permit clock types on some seq operations by @nandor in #6053
• [FIRRTL][IMDCE] Declarations with annotations should not be removed. by @dtzSiFive in #6046
• [FIRRTL][LowerXMR] Handle decls of refs, particularly wires. by @dtzSiFive in #6047
• [FIRRTL][Inliner] Use wires for all. by @dtzSiFive in #6052
• [Seq] Parse registers with a clock type by @nandor in #6062
• [ARC][Seq] Switch arc over to use seq.clock by @nandor in #6054
• [ESI][Runtime] MMIO service support by @teqdruid in #6034
• [NFC] Replace isAnyModule with an isa test. by @darthscsi in #6057
• [FIRRTL][Seq] Lower firrtl.clock to seq.clock by @nandor in #6055
• [InstanceGraph] Add a wrapper for instance paths and fix HW enumeration by @nandor in #6070
• [FIRRTL] Handle duplicate BlackBoxAnnos by @seldridge in #6068
• [FIRRTL] LowerClasses: support ObjectSubfieldOp by @rwy7 in #6064
• [OM][LinkModules] Ignore top-level definitions we don't care about by @rwy7 in #6044
• [FIRRTL][LowerClasses] use early inc range to avoid iter invalidation by @youngar in #6077
• [FIRRTL] Don't canonicalize out-of-bounds subaccess into subindex by @uenoku in #6079
• [FIRRTL] Update LowerClasses to handle property wires. by @mikeurbach in #6067
• [Transforms] Move generally applicable passes to transforms by @mortbopet in #6087
• [FIRRTL] Replace the unrealized conversion cast in LowerXMR with an XMR op by @nandor in #6088
• [FIRRTL][IMCP] Separate materialized constants. by @dtzSiFive in #6090
• [FIRRTL][LowerTypes] Support lowering of wire of ref. by @dtzSiFive in #6048
• [SV][HW] Stable port order in SVExtractTestCode by @seldridge in #6075

Full Changelog: firtool-1.53.0...firtool-1.54.0

Firtool Release 1.53.0

What's Changed

• [FIRRTL] re-work PathOp to use annotations by @youngar in #5933
• [FIRRTL] Add ResolvePathsPass by @youngar in #5942
• [FIRRTL] Add path op parsing by @youngar in #5946
• [FIRRTL] Fix crash resolving annotations through operations w/o "type". by @dtzSiFive in #5948
• [FIRRTL] Bool: type, constant, parser/emitter. by @dtzSiFive in #5956
• [FIRRTL][LowerClasses] Bool support. by @dtzSiFive in #5958
• LLVM bump 08/22/2023 -> 08/25/2023 by @dtzSiFive in #5932
• [FIRRTL] Map: MapCreateOp, parsing support. by @dtzSiFive in #5962
• [FIRRTL][NFC] Automatically register ODS types. by @dtzSiFive in #5968
• [FIRRTL][NFC] Split text for types out from summary if long, tweak. by @dtzSiFive in #5969
• [FIRRTL] getOrAddInnerSym: fix bug when targeting a field by @youngar in #5978
• [firtool] Register conversion passes to make avail for mlir-print-ir. by @dtzSiFive in #5976
• [FIRRTL][InferWidths] Ignore propassign, don't error. by @dtzSiFive in #5984
• [FIRRTL] Support properties in aggregates, remove immediately. by @dtzSiFive in #5993
• [FIRRTL] Support noRefTypePorts in applyGCTMemTaps by @seldridge in #5996
• [FIRRTL][IMCP] Support Properties; support materializing string/bool. by @dtzSiFive in #5994
• [FIRRTL][LowerClasses] Lower map types and map.create by @uenoku in #5997
• [FIRRTL][LowerClasses] Support lowering FIRRTL paths ops to OM by @youngar in #5974
• [FIRRTL, HW] Simplify FieldID support by @darthscsi in #5998
• [FIRRTL] Reject instances of classes. by @dtzSiFive in #6014

Full Changelog: firtool-1.52.0...firtool-1.53.0

SiFive Internal Release 1.5.6

What's Changed

• Backport "[FIRRTL] Prefix for Seq Mem Group Extract (#4596)" to sifive-1.5 by @jackkoenig in #5915
• [ExtractInstances] Fix module prefix not being applied to NLA by @fabianschuiki in #5971

Full Changelog: sifive/1/5/5...sifive/1/5/6