firtool-1.78.1

What's Changed

• [ESI Runtime] If zlib not found, use FetchContent by @teqdruid in #7352
• [Seq] Canonicalize firreg with preset 0 by @prithayan in #7350
• [LLHD] Remove llhd-sim by @maerhart in #7351
• [LLHD] Use hw.inout instead of llhd.sig by @maerhart in #7353
• [LLHD] Replace entity with module by @maerhart in #6958
• [LLHD] Refactor llhd.proc and remove llhd.inst by @maerhart in #7357
• [Handshake] Fix library dependencies by @youngar in #7356
• [FIRRTL] LowerToHW: guard against folded operations by @youngar in #7358
• [firtool] Make layer specialization take a list of layers by @youngar in #7359

Full Changelog: firtool-1.78.0...firtool-1.78.1

firtool-1.78.0

What's Changed

• [CI] Drop macos-11 runners, use macos-12 in uploadReleaseArtifacts by @jackkoenig in #7319
• [llvm] Bump to 0870afaaaccde5b4bae37abfc982207ffafb8332 by @leonardt in #7318
• [MooreToCore] Lower var, read, and assign into LLHD. by @hailongSun2000 in #7297
• [circt-bmc] Add ExternaliseRegisters Pass by @TaoBi22 in #7285
• [Sim] Flatten format string concatenations in canonicalizer by @fzi-hielscher in #7316
• Reland "[FIRRTL][LowerClass] Pre-allocate namespaces before capturing refs (#7102)". by @mikeurbach in #7328
• [Sim] Add printing operations and transformation from non-procedural to procedural flavor by @fzi-hielscher in #7292
• [PyCDE] Simple transforms on channels by @teqdruid in #7330
• [PyCDE] Bundles: coerce method by @teqdruid in #7331
• [ExportVerilog] Add "context" to imported DPI functions by @uenoku in #7333
• [ImportVerilog] Fix unbased unsized literals of packed aggregate type by @fabianschuiki in #7336
• [Verif] Add formal test intent ops by @dobios in #7145
• [ImportVerilog]Dedup module Op by @mingzheTerapines in #7245
• [ImportVerilog] Accept empty packages by @fabianschuiki in #7334
• [ImportVerilog] [SROA] [Mem2Reg][Canonicalizers]Support Passes for Nested Type by @mingzheTerapines in #7158
• [ESI Runtime] Windows: python support and backend plugin loading by @teqdruid in #7338
• [SV] Add UnpackedArrayCreateOp by @uenoku in #7303
• [ImportVerilog] Handle $signed/$unsigned system tasks by @fabianschuiki in #7337
• [FIRRTL][FIRParser] Tokenize Commas by @mmaloney-sf in #7206
• [ImportVerilog] Allow enum variants in expressions by @fabianschuiki in #7339
• [MooreToCore] Support NegOp lowering by @maerhart in #7344
• [FIRRTL] AssignOutputDirs: Ensure absolute dirs end with trailing slash by @rwy7 in #7348

Full Changelog: firtool-1.77.0...firtool-1.78.0

Firtool Release 1.77.0

What's Changed

• [FIRRTL][NFC] Move IST -> FieldRef to FIRRTLUtils.h by @dtzSiFive in #7135
• [Docs][LTL] Add SVA Encodings to LTL rationale by @dobios in #7131
• [FIRRTL] Enable Wire Elimination by @darthscsi in #7073
• Capitalize Mode in github workflow. by @darthscsi in #7140
• [ExportVerilog][HW] Introduce HWEmittableModuleLike interface and use it for Prepare, NFC by @uenoku in #7004
• [FIRRTL][InferResets] Learn how to trace through nodes. by @dtzSiFive in #7141
• [Moore] Introduce RefType and tweak the related ops. by @hailongSun2000 in #7095
• [ExportVerilog] Support sv.func.* op emission by @uenoku in #7015
• [Docs] Update Python bindings pip instructions by @leonardt in #7147
• [Ibis] Divorce symbol and actual names in class and container ops by @mortbopet in #7123
• [FIRRTL] Support abstract reset in RWProbeOp by @dtzSiFive in #7136
• [FIRRTL] Cast to AnyRefType for metadata output port. by @mikeurbach in #7149
• [Handshake] Fix canonicalizer not going through rewriter for RAUW. by @dtzSiFive in #7052
• [MooreToCore] Add conversion support for module and instance. by @cepheus69 in #7132
• [FIRRTL] Emulate tap-as-passive for no-ref-ports option. by @dtzSiFive in #7109
• [FIRRTL][Parser] Never use forceable by @dtzSiFive in #7137
• [FIRRTL] Bump minimum to 2.0.0, remove partial connect by @seldridge in #5075
• [FIRRTL][Metadata] Add the path to the DUT, in the SiFive metadata class. by @prithayan in #7156
• [firtool] Remove LTLToCore pass from verification-flavor=immediate pipeline by @dobios in #7157
• [Moore] Introduce Mem2Reg to eliminate local variables by @hailongSun2000 in #7082
• [Moore] Add the SimplifyProcedures pass. by @hailongSun2000 in #7161
• [Sim] Add DPI func/call and lowering by @uenoku in #7042
• [ExportVerilog] Avoid using interface pass for PrepareForEmission, NFCI by @uenoku in #7168
• [FIRRTL] Add DPI call intrinsic and lowering pass by @uenoku in #7139
• [FIRRTL][ExportVerilog] Emit integers on DPI function as two state C-compatible types and clarify ABI by @uenoku in #7163
• [LowerDPI] Defer deletion of call ops to prevent inavlid access. by @fzi-hielscher in #7170
• [FIRRTL] Add a new op interface for combinational loop detection. by @prithayan in #7120
• [NFC][ExportVerilog] Rename generated options member. by @fzi-hielscher in #7172
• [Moore] Add evenOp to handle event controls. by @hailongSun2000 in #7154
• [ImportVerilog][MooreToCore]Lower moore.namedConstant to hw.constant & hw.wire by @mingzheTerapines in #7122
• Bump llvm by @uenoku in #7167
• [LowerDPI] Refactor the lowering logic to a helper struct, NFC by @uenoku in #7176
• [NFCI][Conversion] Refactor TableGen Pass includes by @fzi-hielscher in #7174
• [NFCI][Calyx] Refactor TableGen Pass includes by @fzi-hielscher in #7182
• [NFCI][Transforms] Refactor TableGen Pass includes by @fzi-hielscher in #7173
• [FIRRTL] Output directory control for layers and modules by @rwy7 in #6971
• [Verif] Add PrepareForFormal pass by @dobios in #7175
• [FIRRTL] Add pass to specialize layers by @youngar in #7160
• Fix paths in tests for windows builds by @rwy7 in #7185
• Add missing header includes by @rwy7 in #7187
• [NFCI][Comb][HW][Seq] Refactor TableGen Pass includes by @fzi-hielscher in #7180
• [NFCI][ESI][Ibis][MSFT] Refactor TableGen Pass includes by @fzi-hielscher in #7179
• [NFCI][LLHD][Moore][SV][Verif] Refactor TableGen Pass includes by @fzi-hielscher in #7183
• [FIRRTL][ExpandWhens] Add StmtExprVisitor to Visitor and Support DPI intrinsic in ExpandWhens by @uenoku in #7177
• [SimToSV] Fix DPICall lowering to use replaceOp by @uenoku in #7192
• [NFCI][FIRRTL] Refactor TableGen Pass includes by @fzi-hielscher in #7178
• [ExportVerilog] Fix two state type emission of aggregate types by @uenoku in #7189
• [FIRRTL][SpecializeLayers] Update doc with proper attribute name by @youngar in #7199
• [NFCI][DC][FSM][Handshake][Pipeline] Refactor TableGen Pass includes by @fzi-hielscher in #7181
• [NFCI][OM][SSP][SystemC] Refactor TableGen Pass includes by @fzi-hielscher in #7184
• [FIRRTL][SpecializeLayers] Fix incorrect CF leading to double free by @youngar in #7200
• [firtool] Move SpecializeLayers before LowerLayers by @youngar in #7201
• [FIRRTL][CheckCombLoops] Verify that detection works with region ops by @youngar in #7198
• [HW] Move the CombDataFlow op interface from FIRRTL to HW by @prithayan in #7195
• [FIRRTL][NFC] Fast-path removeAnnotations for operations having none. by @dtzSiFive in #7203
• [FIRRTL] AnnotationSet cleanups by @youngar in #7205
• [ESI][PyCDE] Callback service by @teqdruid in #7153
• [Moore] Support unconnected behavior by @cepheus69 in #7202
• [CI] Add a job to remove cache created by short integrations tests by @uenoku in #7214
• [Moore] Fix the stacking fault caused by cast and remove unused headers by @hailongSun2000 in #7219
• [FIRRTL] LHSType wrapper to indicate writable values. by @darthscsi in #7117
• [FIRRTL] SpecializeLayers: fix race condition by @youngar in #7218
• [HW] Clean up HWTypes, NFC by @uenoku in #7209
• README.md: remove link to dead build by @youngar in #7222
• [FIRRTL][Verif][LTL] Replace ltl.disable with an enable folded into verif.assert by @dobios in #7150
• [LowerClass] Run path tracking sequentially by @uenoku in #7221
• [ESI Runtime] Replace Cap'nProto with gRPC by @teqdruid in #7217
• [ESI Runtime] Read ports now invoke callbacks by @teqdruid in #7186
• [CI] Revert to working image and disable ESI runtime by @teqdruid in #7237
• [FIRRTL] Allow layers under when and match. by @dtzSiFive in #7234
• [ESI Runtime] Rename cmake targets, create full build one by @teqdruid in #7238
• Bump LLVM by @girishpai in #7223
• [FIRRTL] lower-layers.mlir: fix incorrect op name in test by @youngar in #7232
• [Moore] Add extra class declaration for RefType. by @hailongSun2000 in #7244
• [Interop] Use properties for inherent attributes. by @dtzSiFive in #7235
• [ImportVerilog] Support Generate constructs by @angelzzzzz in #7243
• [NFC][Seq] Remove unnecessary dependency of Seq on SV by @TaoBi22 in #7247
• [NFC][SV] Remove unnecessary dependency of SV on Verif by @TaoBi22 in #7249
• [Moore] Add LowerConcatRef pass to handle concat_ref. by @hailongSun2000 in #7216
• [ESI Runtime][NFC] Incorporate RPC server into ESICppRuntime by @teqdruid in #7241
• [ESI Runtime] Avoid using CIRCT_* cmake variables by @teqdruid in #7256
• [FIRRTL][ResolvePaths] Fix detection of agg target if alias. by @dtzSiFive in #7257
• [MooreToCore] Fix parse error for parameter by @mingzheTerapines in #7253
• [FIRRTL] Ensure hierpath considers owning module in LowerClasses. by @mikeurbach in #7272
• [Arc] Add VectorizeOp canonicalization by @elhewaty in #7146
• [Moore] To make SVModule having a graph region. by @hailongSun2000 in #7258
• [FIRRTL] Add input and output names to DPI intrinsic by @uenoku in #7265
• [ESI Runtime] Load backends as plugins by @teqdruid in #7260
• [PyCDE] R...

Release sifive/1/5/7

What's Changed

• Backport parentheses fix to 1.5.x by @uenoku in #7121

Full Changelog: sifive/1/5/6...sifive/1/5/7

Firtool Release 1.76.0

What's Changed

• [FIRRTL][NFC] Replace intmodules with intrinsic expressions in test. by @dtzSiFive in #7041
• [Arc] Add SplitFuncsPass by @TaoBi22 in #7027
• [Moore] Move IntType definition into ODS by @fabianschuiki in #7035
• [FIRRTL][Intrinsics] source materialization for inferred types. by @dtzSiFive in #7043
• [ESI][Cosim][NFC] Refactor cosim to divorce capnp from DPI by @teqdruid in #7045
• [SV] Add sv.func, sv.return and sv.func.call operations by @uenoku in #7003
• [SV] Add DPI import op by @uenoku in #7005
• [CreateSifiveMetadata] Fix a typo in the field name by @prithayan in #7046
• [SV][Folds] Fix ForOp canonicalizer to use rewriter. by @dtzSiFive in #7048
• [HW] Fix pattern returning success() without changing. by @dtzSiFive in #7053
• [Comb] Fix MuxRewriter to eraseOperand in rewriter-aware way. by @dtzSiFive in #7054
• [LLHD] Fix operand assignments not going through rewriter. by @dtzSiFive in #7055
• FileCheck directive fixup, now filecheck_lint-clean. by @dtzSiFive in #7057
• [Moore] Simplify and move RealType definition into ODS by @fabianschuiki in #7036
• [ESI][Runtime] Refactor cosim backend to be thread safe by @teqdruid in #7059
• [FIRRTL] Fix width of attribute in MuxPadSel canonicalizations. by @dtzSiFive in #7056
• [FIRRTL,PASS] Simple module summary looking for likely to dedup larger or numerous modules. This is to guide developers in using chisel better. by @darthscsi in #6935
• [FIRRTL][Import] Remove support for printf-encoded verif. by @dtzSiFive in #7030
• [FIRRTL][Folds] Fix patterns to use rewriter for RAUW by @dtzSiFive in #7049
• [LTL] Add repeat and until operators by @liuyic00 in #6989
• [FIRRTL] Reject intrinsic modules >= 4.0.0 by @dtzSiFive in #7009
• [PyCDE] Move build and publishing pipeline into repo by @teqdruid in #7062
• [FIRRTL][LowerClasses] Improve performance, NFC by @uenoku in #7060
• [FIRRTL] Convert Wires into Nodes by @darthscsi in #7067
• [FIRRTL] Register reset elimination based on invalid can look through nodes. by @darthscsi in #7069
• [FIRRTL] Remove unused and expensive API, NFC by @uenoku in #7076
• [FIRRTL] Preserve all analysis if nothing happens by @uenoku in #7077
• [FIRRTL] Limited invalid propagation. by @darthscsi in #7074
• LLVM bump by @youngar in #7079
• [ImportVerilog] Support member-access expression by @mingzheTerapines in #7039
• [ImportVerilog] Support set membership operator. by @angelzzzzz in #7066
• [LowerClasses] Ensure classes are instantiated by an object. by @prithayan in #7072
• [Verif] Add clocked Assert Assume Cover ops by @dobios in #7022
• [LTL] Add ops that allow for most of SVA to be modeled with LTL by @dobios in #7065
• [Seq] Fix incorrect folder by @uenoku in #7085
• [Arc] Modify VectorizeOp to support AnyType by @elhewaty in #7087
• [Moore] Move array types into ODS by @fabianschuiki in #7088
• [Moore] Support stripped type parsing and printing by @fabianschuiki in #7090
• [Moore] Move struct types into ODS by @fabianschuiki in #7091
• [Arc] Initial SLP support by @elhewaty in #7061
• [SMT] Added support for :pattern attribute by @luisacicolini in #6976
• [FIRRTL] Drop Hoistpassthroughs pass. by @dtzSiFive in #7097
• [CombToSMT] Register dependency on func by @maerhart in #7098
• [firtool] Add an option to export SV without SVA by @dobios in #7081
• [Arc] Fix crashes in FindInitialVectors Pass by @elhewaty in #7100
• [ImportVerilog][Moore] Support union type by @mingzheTerapines in #7084
• [FIRRTL][LowerClass] Pre-allocate namespaces before capturing references by @uenoku in #7102
• LLVM bump by @debs-sifive in #7103
• [ImportVerilog] Support parameter constants. by @angelzzzzz in #7083
• [FIRRTL] Visitor: Add missing ops, fix GenericIntrinsicOp visit. by @dtzSiFive in #7107
• [FIRRTL] Generate memportaccess op index as UInt. by @dtzSiFive in #7108
• CMake: Fix CIRCT_ENABLE_FRONTENDS to be string not bool. by @dtzSiFive in #7110
• [Arc] Add statistics to the FindInitialVectors pass by @elhewaty in #7113
• [NFC, FIRRTL] Rename StrictConnect to MatchingConnect. by @darthscsi in #7116
• [FIRRTL] Simplify path handling in ResolvePaths and LowerClasses. by @mikeurbach in #7129
• [FIRRTL] Actually copy the leading part of the path in LowerClasses. by @mikeurbach in #7130
• [Moore] Add module and instance port support by @fabianschuiki in #7112
• [FIRRTL][DropConst] Fix performance with many extmodule's. by @dtzSiFive in #7126
• [ImportVerilog] Add conditional operator. by @angelzzzzz in #6950

New Contributors

• @liuyic00 made their first contribution in #6989
• @mingzheTerapines made their first contribution in #7039
• @elhewaty made their first contribution in #7087

Full Changelog: firtool-1.75.0...firtool-1.76.0

Firtool Release 1.75.0

What's Changed

• [FIRRTL] Canoncializations of not( cmp ) by @darthscsi in #6957
• Fix invalid rewriter API usages by @7FM in #6960
• [NFC] LLVM Bump by @darthscsi in #6963
• [HW] Moved and renamed arc/inlineModules to hw/flattenModules by @dobios in #6964
• [firtool] btor2 integration by @dobios in #6947
• [ExportVerilog] Ensure DivS/ModS are signed regardless of context. by @dtzSiFive in #6966
• [FIRRTL][FIRParser] Add deprecation warning about printf/when-encoding. by @dtzSiFive in #6792
• [FIRRTL] Error if asked to add a port to a public module. by @dtzSiFive in #6936
• [Seq] Fix compreg printer printing two spaces by @Moxinilian in #6978
• [FIRRTL] Drop dead ScalaClassAnnotation. by @dtzSiFive in #6981
• [FIRRTL] Add inline convention to layers by @seldridge in #6980
• [SMT] Add quantifier support to LLVM lowering by @maerhart in #6973
• [Arc] Hoist reset value in CompReg when lowering for simulation by @Moxinilian in #6972
• [LTL to Core] Add lowering for AssertProperty operations by @dobios in #6974
• [NFCI] Document division and the rational for the handling of divide by zero by @darthscsi in #6962
• [FIRRTL] docs: fullasync annotation targets signal not module. by @dtzSiFive in #6986
• [firtool] Integrate AssertProperty lowering into BTOR2 pipeline by @dobios in #6975
• [FIRRTL][InferResets] Fix fullasyncreset diag to use right name. by @dtzSiFive in #6987
• [FIRRTL][Dedup] Alter dedup group handling, avoid exponential behavior. by @dtzSiFive in #6985
• [CombToArith] Fix coarsening of division by zero UB by @maerhart in #6945
• [Pipeline] Verify >0 result types for LatencyOp by @mortbopet in #6992
• [DC] Add merge lowering by @mortbopet in #6943
• [Handshake] Add merge decomposition pattern by @mortbopet in #6934
• [CAPI][Moore] Remove deprecated types by @hovind in #6994
• [FIRRTL][LowerAnnotations] Reject non-local fullasyncreset anno's. by @dtzSiFive in #6988
• [NFC][clang-tidy] Disallow global 'using' directives in headers by @fzi-hielscher in #6998
• [FIRRTL][SFCCompat] Fix tests and handling of fullasyncreset on non-port. by @dtzSiFive in #6984
• [pycde] Disallow structs with zero fields by @teqdruid in #7000
• [ImportVerilog] Fix unknown name caused by local variables. by @hailongSun2000 in #6995
• [firtool] Add FlattenModulesPass to the btor2 emission pipeline by @dobios in #6999
• [FIRRTL][NFC] Drop use of intmodule's in tests. by @dtzSiFive in #7008
• [FIRRTL][LowerIntrinsics] Add stat and preserve if no changes. by @dtzSiFive in #6911
• [FIRRTL] AnnoTarget: use LLVM style casts by @youngar in #7002
• LLVM Bump by @dobios in #6993
• [HW][LegalizeModules] Avoid segmentation fault by @hovind in #7013
• [FIRRTL] Make input probes illegal by @dtzSiFive in #6921
• [FIRRTL] Don't prefix an empty label for unclocked assume. by @dtzSiFive in #7016
• [CAPI] Add circt-capi target and build it in CI by @fabianschuiki in #7017
• [docs] Add cmake flags that reduce memory usage by @dobios in #7018
• [HWToSMT][circt-lec] Resolve transitive !smt.bool -> i1 -> !smt.bv<1> casts. by @fzi-hielscher in #7006
• [ARC][CAPI] Add basic C API for initializing ARC by @devins2518 in #6997
• [Moore] Make simple bit vectors a proper MLIR type by @fabianschuiki in #7011
• [AddSeqMemPorts] Add hierpathop to verbatim, instead of raw instance path by @prithayan in #7014
• [docs] Add basic pass tutorial by @dobios in #7012
• [FIRRTL] Add condition expansion for ExpandWhens on Property intrinsics by @dobios in #7021
• [OM] Add IsolatedFromAbove to OMClass by @uenoku in #7020
• [ESI][Runtime] Python wheel now provides cpp support by @teqdruid in #7001
• cmake: circt install directory for CAPI by @dtzSiFive in #7028
• [ESI][Runtime] Remove C++ includes from wheels by @teqdruid in #7032
• [OM] Separates OM object fields verifier to a dedicated pass by @uenoku in #7026
• [SV] Add sv.reserve_names op to disallow names by @teqdruid in #7024
• [ESI][Runtime] Don't pull down JSON dependency if already defined by @teqdruid in #7033
• [CombToSMT] Make result of div-by-zero undefined by @maerhart in #7025

Full Changelog: firtool-1.74.0...firtool-1.75.0

Firtool Release 1.74.0

What's Changed

• [FIRRTL] Gather intrinsic lowering via dialect interface. by @dtzSiFive in #6923
• [FIRRTL] no back-prop for width of mux selectors, support narrower by @dtzSiFive in #6917
• Update annotation handling to fix partial field reset behavior by @adkian-sifive in #6912
• [Arc] Fix segfault in SplitLoops by @Moxinilian in #6928
• [HWToBTOR2] Deduce resets from (Fir)RegOps by @TaoBi22 in #6918
• Bump llvm by @azidar in #6932
• [FIRRTL] Disambiguate paths when possible in ResolvePaths. by @mikeurbach in #6937
• [SMT] Added weight attribute support for ExportSMTLIB by @luisacicolini in #6920
• [SMT] Add lowering to LLVM IR by @maerhart in #6902
• [SMTToLLVM] Add support for most expressions by @maerhart in #6905
• [circt-lec] Port to SMT dialect based compiler pipeline by @maerhart in #6908
• [ImportVerilog] Add replicate and extract operations. by @hailongSun2000 in #6906
• [ImportVerilog] Add case statement. by @angelzzzzz in #6929
• [ImportVerilog] Fix the types mismatch for variable declarations. by @hailongSun2000 in #6907
• [Moore] Introduce a new operation - netOp for net declaration by @cepheus69 in #6884
• [FIRRTL][CAPI] Add function for getting mask type by @SpriteOvO in #6944
• [HandshakeToDC] Fix constant unit-rate op lowering by @mortbopet in #6942
• [Comb] Remove more idempotent operands by @hovind in #6903
• [MooreToCore] Lower moore operators into comb or hw. by @hailongSun2000 in #6940
• [Scheduling] computeStartTimesInCycle: clear before recomputation by @7FM in #6951
• [FIRRTL] Don't fail compilation when Dedup group annotation is on EICG_wrapper by @uenoku in #6955

New Contributors

• @luisacicolini made their first contribution in #6920
• @hailongSun2000 made their first contribution in #6906
• @angelzzzzz made their first contribution in #6929

Full Changelog: firtool-1.73.0...firtool-1.74.0

firtool-1.73.0

What's Changed

• [Pipeline] Remove Pure trait from Pipeline operations by @mortbopet in #6888
• [Ibis] Introduce 'ibis.design' by @teqdruid in #6835
• [Ibis] fix invalid std::optional dereferencing by @mortbopet in #6895
• Bump LLVM to latest by @seldridge in #6894
• [FIRRTL] Fixup visit ops miscategorized. by @dtzSiFive in #6896
• [FIRRTL][NFC] Remove dead signal driving annos. by @dtzSiFive in #6898
• [FIRRTL] Drop support for long-unused subcircuit annotations. by @dtzSiFive in #6899
• [SMT] Minor width related fixes for BitVectorAttr by @fzi-hielscher in #6900
• [LowerToHW] Wrap signed operands of PrintFOp in sv $signed() by @ubfx in #6887
• [FIRRTL][CAPI] Allow constructing integers larger than 64 bits by @SpriteOvO in #6893
• [FIRRTL] Use a flag to implement scalarization of internal modules. … by @darthscsi in #6901
• [FIRRTL] Generic intrinsic parsing/emitter support by @dtzSiFive in #6897
• [CreateSiFiveMetadata] Generate firrtl.class instead of om.class by @prithayan in #6736
• [LowerFirReg] Reimplement the mux reachability analysis by @prithayan in #6709
• [FIRRTL] LowerIntrinsics: rewrite to lower generic ops. by @dtzSiFive in #6877
• [FIRRTL][LowerIntmodules] Add stats, preserve if nothing changed. by @dtzSiFive in #6910
• [Ibis] Divorce port name (hints) from port symbol names by @mortbopet in #6909
• [LowerFirReg] Reimplement the mux reachability analysis by @prithayan in #6914
• llvm: bump by @dtzSiFive in #6915
• [FIRRTL][NFC] Use underscores in documentation. by @dtzSiFive in #6860

Full Changelog: firtool-1.72.0...firtool-1.73.0

Firtool Release 1.72.0

I messed up https://github.com/llvm/circt/releases/tag/firtool-1.71.0, sorry! This contains the correct (and many repeated) commits.

What's Changed

• [NFC] Move 'using namespace' out of headers. by @fzi-hielscher in #6844
• [FSM][Emit] Convert the FSMToSV pass to use emit ops by @nandor in #6828
• [Emit][Seq] Emit random init headers using fragments by @nandor in #6826
• [HW][IST] Verify simple inner-ref-user ops sequentially, perf fix. by @dtzSiFive in #6850
• Fix a few FileCheck directive typos. by @dtzSiFive in #6853
• [FIRRTL][NFC] Move xmr.ref and xmr.deref into expressions. by @dtzSiFive in #6852
• [circt-lec] Add ConstructLEC pass by @maerhart in #6833
• StripDebugInfoWithPred: Fix parallelization perf issue. by @dtzSiFive in #6851
• [ImportVerilog] Add if and loop statements by @fabianschuiki in #6831
• [FIRRTL] Remove support for circt.Intrinsic annotation. by @dtzSiFive in #6857
• [FIRRTL] Make "intrinsic" name of intmodule mandatory. by @dtzSiFive in #6858
• [Docs] Extend formal verification documentation by @maerhart in #6854
• [Seq] Erase memories with no read ports by @nandor in #6861
• [ImportVerilog] Add assign and pre/post increment/decrement expressions by @fabianschuiki in #6859
• [SMT] Add quantifier operations by @maerhart in #6842
• [SMT] Add function application operation, function and uninterpreted sort types by @maerhart in #6847
• [SV][Verif] Extract verif ops in SVExtractTestCode by @seldridge in #6865
• [NFCI] Declare common attributes for fmodule* by @darthscsi in #6868
• [FIRRTL] Cache a symbol table instead of doing linear lookups every instance. by @darthscsi in #6871
• [LowerToHW] Set fragments outside the parallel region by @nandor in #6872
• [SMT] Add SMT-LIB export translation by @maerhart in #6870
• [FIRRTL] Add generic intrinsic op. by @dtzSiFive in #6874
• [FIRRTL] Add LowerIntmodules pass. by @dtzSiFive in #6876
• [FIRRTL] Change Port Direction attribute from an APInt to a DenseArray. by @darthscsi in #6875
• [FIRRTL] Add intrinsic for UNR only assume by @uenoku in #6867
• [FIRRTL] Add CreateCompanionAssume pass; Decouple UNROnlyAssume generation from AssertOp lowering by @uenoku in #6863
• [NFC] Make fewer copies of directions by @darthscsi in #6879
• [Docs] GettingStarted: Fix images and LLVM/MLIR contributing guide by @ubfx in #6873
• [FIRRTL] Deprecate AssertAssume intrinsic and rename it to Assert by @uenoku in #6878
• [Docs] Correct a typo in circt-lec/README.md by @felixonmars in #6849
• [FIRRTL] Treat blackboxes in layers as "testbench" by @seldridge in #6881
• [SeqToSV] Fix the ordering of the memory/register random init fragments by @nandor in #6883
• [NFC] Massive Export Verilog Speedup by @darthscsi in #6886
• [LowerToHW] Emission Option for verification flavors by @uenoku in #6885
• [FIRRTL] Expose clock dividers as a FIRRTL intrinsic by @nandor in #6890
• [CFToHandshake] Move Transforms dependency to implementation by @mortbopet in #6889
• [NFC] Cache common lookups in ModuleType by @darthscsi in #6892

New Contributors

• @ubfx made their first contribution in #6873
• @felixonmars made their first contribution in #6849

Full Changelog: firtool-1.70.0...firtool-1.72.0

Firtool Release 1.71.0

What's Changed

• [NFC] Move 'using namespace' out of headers. by @fzi-hielscher in #6844
• [FSM][Emit] Convert the FSMToSV pass to use emit ops by @nandor in #6828
• [Emit][Seq] Emit random init headers using fragments by @nandor in #6826
• [HW][IST] Verify simple inner-ref-user ops sequentially, perf fix. by @dtzSiFive in #6850
• Fix a few FileCheck directive typos. by @dtzSiFive in #6853
• [FIRRTL][NFC] Move xmr.ref and xmr.deref into expressions. by @dtzSiFive in #6852
• [circt-lec] Add ConstructLEC pass by @maerhart in #6833
• StripDebugInfoWithPred: Fix parallelization perf issue. by @dtzSiFive in #6851
• [ImportVerilog] Add if and loop statements by @fabianschuiki in #6831
• [FIRRTL] Remove support for circt.Intrinsic annotation. by @dtzSiFive in #6857
• [FIRRTL] Make "intrinsic" name of intmodule mandatory. by @dtzSiFive in #6858
• [Docs] Extend formal verification documentation by @maerhart in #6854
• [Seq] Erase memories with no read ports by @nandor in #6861
• [ImportVerilog] Add assign and pre/post increment/decrement expressions by @fabianschuiki in #6859
• [SMT] Add quantifier operations by @maerhart in #6842
• [SMT] Add function application operation, function and uninterpreted sort types by @maerhart in #6847
• [SV][Verif] Extract verif ops in SVExtractTestCode by @seldridge in #6865

Full Changelog: firtool-1.70.0...firtool-1.71.0