Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
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Updated
May 8, 2024 - Verilog
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
Pre and Post Synthesis Simulation of a Design VSDMemSOC
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
Practice Codes of Verilog Language
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.
Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)
A place to keep my synthesizable verilog examples.
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.
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