#

hardware-description-language

Here are 136 public repositories matching this topic...

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Nov 2, 2024
Haskell

drom / awesome-hdl

Hardware Description Languages

awesome vhdl verilog awesome-list hdl hacktoberfest hardware-description-language

Updated Aug 18, 2024

JulianKemmerer / PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

python c fpga hls hardware vhdl pipelines open-source-hardware high-level-synthesis hardware-description-language fpga-accelerators fpga-acceleration fpga-programming hardware-description

Updated Nov 2, 2024
Python

WangXuan95 / BSV_Tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

fpga verilog bluespec hdl bluespec-systemverilog bsv hardware-description-language

Updated Sep 15, 2023
Bluespec

jofrfu / tinyTPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Updated Jan 5, 2019
VHDL

SystemRDL / systemrdl-compiler

SystemRDL 2.0 language compiler front-end

asic fpga eda csr registers systemrdl register-descriptions systemrdl-compiler hardware-description-language design-automation register-description-language

Updated Sep 3, 2024
Python

cucapra / filament

Fearless hardware design

fpga type-system hardware-description-language hardware-accelerator

Updated Nov 1, 2024
Verilog

mit-plv / kami

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

coq proof-assistant bluespec hardware-description-language hardware-verification

Updated Sep 23, 2024
Coq

mit-plv / koika

A core language for rule-based hardware design 🦑

semantics coq programming-languages formal-methods compilation hardware-description-language

Updated Oct 13, 2024
Coq

cyber-anubis / The-HACK-General-Purpose-Computer

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone compute…

cpu compiler virtual-machine assembler operating-system nand2tetris computer-architecture nand machine-language hardware-description-language arithmetic-logic-unit

Updated Oct 2, 2020
Python

SystemRDL / PeakRDL

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

Updated Sep 3, 2024
Python

asyncvlsi / act

ACT hardware description language and core tools.

language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes

Updated Oct 30, 2024
C++

pc2 / sus-compiler

A new Hardware Design Language that keeps you in the driver's seat

programming-language tree-sitter fpga hdl hardware-description-language fpga-programming

Updated Nov 2, 2024
Rust

mikeroyal / VHDL-Guide

VHDL Guide

awesome fpga hardware vhdl verilog awesome-list hardware-designs vhdl-modules awesome-resources hardware-description-language vhdl-elearning vhdl-examples vhdl-coursework

Updated Jan 3, 2022
VHDL

tharunchitipolu / Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

rtl verilog fulladder vlsi multiplier hardware-description-language wallace vlsi-design vlsi-project dadda-tree carry-save-adder fast-multiplication dadda-multiplier tree-multipliers

Updated Jun 6, 2024
Verilog

JeffDeCola / my-verilog-examples

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated Jul 10, 2023
Verilog

drom / reqack

🔁 elastic circuit toolchain

verilog hdl hacktoberfest hardware-description-language

Updated Apr 22, 2022
JavaScript

GSimas / INE5406

📚Repositório da Disciplina INE5406 - Sistemas Digitais

design automation fpga vhdl eda circuits electronic rtl sistemas electrical-engineering ufsc digitais digital-systems quartus hardware-description-language ine5406

Updated Jun 21, 2018
HTML

fayizferosh / yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools

Updated Oct 18, 2023
Verilog

chaseruskin / legoHDL

An experimental package manager and development tool for Hardware Description Languages (HDL).

package-manager fpga vhdl verilog digital-logic hdl digital-design hardware-description-language hardware-design

Updated Apr 10, 2022
Python

Improve this page

Add a description, image, and links to the hardware-description-language topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the hardware-description-language topic, visit your repo's landing page and select "manage topics."