Guitar triggered PLL Synth effect

GPS disciplined oscillator project aims to create a clock source device with eight 10MHz outputs adjust by the 1PPS signal from the GGPS/GNSS module and PLL circuit.

LM7001 to Si4703 FM tuner bridge

Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.

TSA5511 PLL Controller for Arduino

Train your PLL skills on Rubik's cube with this groovy script

This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm technology node

A 3x3 rubik's cube solver made with python using the CFOP method.

Firmware (Sketch) for Arduino MEGA DDS (Direct Digital Synthesis) Analog Devices AD9915 Arduino Shield by GRA & AFCH

All Digital Phase-Locked Loop

This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.

Rubik's cube solver using CFOP

A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

Grafico PLL animato in C++

Data and code to design and evaluate the PLL-based true random number generator according to the paper "Enhancing Quality and Security of the PLL-TRNG" (published and awarded at TCHES 2023).

Library for ICS501.

Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process

Design and generate the GDSII file for an 8x PLL Clock Multiplier IP with open source PDK & tools

Alternative version of the MTS module (https://github.com/TU-Darmstadt-APQ/MTS_module) for 80 MHz and 200 MHz AOMs.

Three phase (3PH) DSOGI Phase Lock Loop (PLL)