A VHDL implementation of the mini-game Genius.

This repo consists of 6 projects implemented with Verilog language, ModelSim environment, and Quartus.

A RISC-V Microprocessor

Ein 2-Kanal-Funktionsgenerator mittels Direct Digital Synthesis (DDS). Erstellt als Gruppenprojekt für das Modul BTE5024 – Anwendungen elektronischer Systeme.

Metronome FPGA implementation controlled from PC

Control Unit implementation for FPGA in VHDL

Simple test for interfacing FPGA and SoC on a de10 nano board

Final Project for Digital System Lab. Flappy Bird Imitation Game created using VHDL for FPGA DE1.

Documentation:

Descrição de Hardware realizado na matéria Projeto de Sistemas Digitais

The first lab of the course, ECE 5760

Atari River Raid game programming project using VHDL programming language and FPGA Quartus board

Computer Architecture - Practical Solution with Quartus - Sharif University of Technology

Implementation of MIPS architecture using Quartus II and Verilog

FPGA based GPU for rendering ray marched scenes.

Experiments for "Digital Systems Design Lab".

🐦 Flappy Bird implemented in VHDL for SSC-108 - Digital Systems @ University of São Paulo