risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 56 public repositories matching this topic...
Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg
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Mar 6, 2019 - VHDL
A small RISC-V core (VHDL)
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Dec 3, 2019 - VHDL
A RISC-V 32bit processor implementation with a minimal set of Instructions.
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Dec 16, 2020 - VHDL
Trabalho de Organização e Arquitetura de Computadores, UnB - 2020/2
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May 23, 2021 - VHDL
EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and imp…
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Jul 19, 2021 - VHDL