An abstraction library for interfacing EDA tools
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Updated
May 17, 2024 - Python
An abstraction library for interfacing EDA tools
pulp_soc is the core building component of PULP based SoCs
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
Repurposing existing HDL tools to help writing better code
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
Control and status register code generator toolchain
CoreIR Symbolic Analyzer
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Python library for parsing module definitions and instantiations from SystemVerilog files
Python/Simulator integration using procedure calls
This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
SystemVerilog & Verilog Module I/O parser and printer
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