systemverilog
Here are 54 public repositories matching this topic...
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
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Jun 3, 2024 - Python
A flexible and scalable development platform for modern FPGA projects.
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May 31, 2024 - Python
pulp_soc is the core building component of PULP based SoCs
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May 31, 2024 - Python
Repurposing existing HDL tools to help writing better code
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May 24, 2024 - Python
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
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May 21, 2024 - Python
An opinionated build environment for EDA projects
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May 21, 2024 - Python
An abstraction library for interfacing EDA tools
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May 17, 2024 - Python
Making cocotb testbenches that bit easier
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May 15, 2024 - Python
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
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May 5, 2024 - Python
A tool for the creation of JasperGold SVP principle tcl files.
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Apr 23, 2024 - Python
Packed data structure specifications for multi-language hardware projects.
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Apr 28, 2024 - Python
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
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May 14, 2024 - Python
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
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Mar 29, 2024 - Python
Generate the uvm testbench automatically
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Mar 27, 2024 - Python
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
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Mar 18, 2024 - Python
VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.
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Feb 4, 2024 - Python
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