Basic Stopwatch Design using Terasic DE-10 Standard FPGA
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Updated
Jul 30, 2022 - SystemVerilog
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
Here you'll find the game "Donkey Kong" written 100% in SysVerilog. You'll need an FPGA card, a screen, a keyboard, and audio devices for the full functionality.
A single SystemVerilog package with both classes of half as well as full adder is created and tested using the testbench
Single-cycle single-core MIPS processor
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
For finalizing experimental development work on the mksocfpga_hm3 repo back into machinekit
This repository is my shot at SV and UVM for basic Design & Verification data structures
Implements instruction split, opcode and alucontrol codes generation.
Design and verification of first come first serve arbiter
I made a motion controlled digital synthesizer known as a puppeteer theremin that uses AI to get motion control data from a server hosted on a phone onto an FPGA.
Designing simple 5-stage pipelined RISC-V processor (Lab assignment of "Computer Architecture" class)
About Coursework 2 for ELEC70056: Hardware and Software Verification, Hardware Component - Verification of SystemVerilog designs using assertions and timing statements
Coverage, Assertions, Randomizations, Mailbox, Semaphores, DPI and OOP: Inheritance, Polymorphism, Virtual methods
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