RISC-V pipeline research: RV32IM soft core, branch prediction (SGF), FPGA experiments + paper
-
Updated
May 28, 2026 - SystemVerilog
RISC-V pipeline research: RV32IM soft core, branch prediction (SGF), FPGA experiments + paper
Cycle-approximate out-of-order RISC-V CPU simulator with TAGE branch prediction, store-to-load forwarding, and a genetic algorithm for design space exploration using real CoreMark execution.
Add a description, image, and links to the tage topic page so that developers can more easily learn about it.
To associate your repository with the tage topic, visit your repo's landing page and select "manage topics."