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ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Verilog/SystemVerilog modules and finally generating a CSV file containing several components of the generated power, timing, and utilization reports.
This project provides a TCL command for PrimeTime, enabling a straightforward implementation of a post-synthesis leakage power minimization procedure. Developed as part of a contest project for the course "Synthesis and Optimization of Digital Circuits" at Politecnico di Torino. This tool is designed to streamline power optimization efforts.
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design