tcl

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

fpga cpp matlab tcl verilog

Updated Jul 21, 2023
Verilog

addisonElliott / SCIC

Star

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

asic cpu digital simulation tcl rtl verilog synthesis icarus-verilog gate cadence

Updated Nov 29, 2018
Verilog

fayizferosh / yosys-tcl-ui-report

Star

5 Day TCL begginer to advanced training workshop by VSD

linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools

Updated Oct 18, 2023
Verilog

gabrielganzer / RTL-PowerOptimization

Star

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

script optimization polito tcl project synopsys dvs primetime voltage-scaling design-vision synopsys-dc

Updated Jun 9, 2021
Verilog

chipsalliance / f4pga-xc-fasm2bels

Star

Library to convert a FASM file into BELs importable into Vivado.

tcl verilog vivado fasm bitstream artix-7 symbiflow

Updated Sep 25, 2023
Verilog

andrea4g / low_power_contest

Star

Master degree project for Synthesis and Optimization of Digital Systems

optimization polito tcltk tcl synthesis synopsys low-power

Updated Feb 16, 2018
Verilog

gabrielganzer / VHDL-DesignSynthesis

Star

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

polito vhdl scripts tcl rtl verilog synthesis digital-design control-unit subtractor physical-design booth-multiplier register-file windowed-register-file adder-subtractor

Updated Jan 24, 2021
Verilog

AkshayXPatil / MSDAP

Star

Complete design of a Mini Stereo Digital Audio Processor

asic perl scripting tcl rtl convolution fir-filter gdsii

Updated Jan 3, 2019
Verilog

thegabriele97 / TCL-Learning

Star

Contains some TCL scriping language excercises + 2 university contests on HIgh Level Synthesis (winner contest) and Logic Level Synthesis

tcl

Updated Jul 10, 2021
Verilog

Dany2002-hub / Vivado_Scripting_and_Automation

Star

ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Verilog/SystemVerilog modules and finally generating a CSV file containing several components of the generated power, timing, and utilization reports.

python shell automation scripting jupyter-notebook tcl verilog vivado systemverilog