OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
-
Updated
Sep 23, 2024 - Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
AMC: Asynchronous Memory Compiler
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
genetic algorithm usage for routing optimization ( pyqt )
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
Micro-Framework for FPGA / VLSI Design Flow in Python
Gate-level visualization generator for SKY130-based chip designs.
Combinatorial Decision Making and Optimization project on Very Large Scale Integration (VLSI) with Constraint Programming (CP), propositional SATisfiability (SAT), and Satisfiability Modulo Theories (SMT)
The VLSI problem requires to fit all the rectangles in the grid without overlapping one on an another, by minimizing the height of the grid.
RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
Solving The VLSI (Very Large Scale Integration) optimization problem using constraint programming and SMT.
Given a simple VLSI (Very Large Scale Integration), use Constraint Programming, SAT and SMT solver, to provide the solution with the minimum height of the silicon chip
Simple EDA tool for fault reduction and testing for combinational circuits
Add a description, image, and links to the vlsi topic page so that developers can more easily learn about it.
To associate your repository with the vlsi topic, visit your repo's landing page and select "manage topics."