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SETSSBSY

Henk-Jan Lebbink edited this page Jun 4, 2026 · 1 revision

SETSSBSY — Mark Shadow Stack Busy

Opcode/ Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description
F3 0F 01 E8 SETSSBSY ZO V/V CET_SS Set busy flag in supervisor shadow stack token reference by IA32_PL0_SSP.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
ZO N/A N/A N/A N/A

Description

The SETSSBSY instruction verifies the presence of a non-busy supervisor shadow stack token at the address in the IA32_PL0_SSP MSR and marks it busy. Following successful execution of the instruction, the SSP is set to the value of the IA32_PL0_SSP MSR.

This instruction cannot be executed when FRED transitions are enabled. FRED transitions do not use supervisor shadow stack tokens.

Operation

IF CR4.CET = 0 OR CR4.FRED = 1
    THEN #UD; FI;
IF IA32_S_CET.SH_STK_EN = 0
    THEN #UD; FI;
IF CPL > 0
    THEN GP(0); FI;
SSP_LA = IA32_PL0_SSP
If SSP_LA not aligned to 8 bytes
    THEN #GP(0); FI;
expected_token_value = SSP_LA
                            (* busy bit must not be set *)
new_token_value          = SSP_LA | BUSY_BIT
                            (* set busy bit; bit position 0 *)
IF shadow_stack_lock_cmpxchg8B(SSP_LA, new_token_value, expected_token_value) != expected_token_value
    THEN #CP(SETSSBSY); FI;
SSP = SSP_LA

Flags Affected

None.

C/C++ Compiler Intrinsic Equivalent

SETSSBSYvoid _setssbsy(void);

Protected Mode Exceptions

#UD If the LOCK prefix is used. If CR4.CET = 0. IF IA32_S_CET.SH_STK_EN = 0.

#GP(0) If IA32_PL0_SSP not aligned to 8 bytes. If CPL is not 0.

#CP(setssbsy) If busy bit in token is set. If the address in token is not below 4 GBytes.

#PF(fault-code) If a page fault occurs.

Real-Address Mode Exceptions

#UD The SETSSBSY instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#UD The SETSSBSY instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD If the LOCK prefix is used. If CR4.CET = 0. IF IA32_S_CET.SH_STK_EN = 0. If CR4.FRED = 1.

#GP(0) If IA32_PL0_SSP not aligned to 8 bytes. If CPL is not 0.

#CP(setssbsy) If busy bit in token is set. If the address in token is not below 4 GBytes.

#PF(fault-code) If a page fault occurs.

64-Bit Mode Exceptions

Same as compatibility mode exceptions (except there is no check on the token address).


Source: Intel® 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes (Order Number 325462-091US, March 2026)
Generated: 7-6-2026

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