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VSM3RNDS2

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Henk-Jan Lebbink edited this page Jun 4, 2026 · 1 revision

VSM3RNDS2 — Perform Two Rounds of SM3 Operation

Opcode/ Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description
VEX.128.66.0F3A.W0 DE /r /ib VSM3RNDS2 xmm1, xmm2, xmm3/m128, imm8 AV/V AVX SM3 Performs two rounds of SM3 operation using the initial SM3 states from xmm1 and xmm2, and pre-computed words from xmm3/m128, storing the result in xmm1.

Instruction Operand Encoding

Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4
A N/A ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) imm8

Description

The VSM3RNDS2 instruction performs two rounds of SM3 operation using initial SM3 state (C, D, G, H) from the first operand, an initial SM3 states (A, B, E, F) from the second operand and a pre-computed words from the third operand. The first operand with initial SM3 state of (C, D, G, H) assumes input of non-rotated left variables from previous state. The updated SM3 state (A, B, E, F) is written to the first operand.

The imm8 should contain the even round number for the first of the two rounds computed by this instruction. The computation masks the imm8 value by AND’ing it with 0x3E so that only even round numbers from 0 through 62 are used for this operation.

Operation

//see the VSM3MSG1 instruction for definition of ROL32()
define P0(dword):
    return dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)
define FF(x,y,z, round):
    if round < 16:
        return (x ^ y ^ z)
    else:
        return (x & y) | (x & z) | (y & z)
define GG(x,y,z, round):
    if round < 16:
        return (x ^ y ^ z)
    else:
        return (x & y) | (~x & z)

VSM3RNDS2 SRCDEST, SRC1, SRC2, IMM8

A[0] ← SRC1.dword[3]
B[0] ← SRC1.dword[2]
C[0] ← SRCDEST.dword[3]
D[0] ← SRCDEST.dword[2]
E[0] ← SRC1.dword[1]
F[0] ← SRC1.dword[0]
G[0] ← SRCDEST.dword[1]
H[0] ← SRCDEST.dword[0]
W[0] ← SRC2.dword[0]
W[1] ← SRC2.dword[1]
W[4] ← SRC2.dword[2]
W[5] ← SRC2.dword[3]
C[0] ← ROL32(C[0], 9)
D[0] ← ROL32(D[0], 9)
G[0] ← ROL32(G[0], 19)
H[0] ← ROL32(H[0], 19)
ROUND ← IMM8 & 0x3E // even numbers 0...62
IF ROUND < 16:
    CONST ← 0x79cc4519
ELSE:
    CONST ← 0x7a879d8a
CONST ← ROL32(CONST,ROUND)
FOR i in 0..1:
    S1 ← ROL32((ROL32(A[i], 12) + E[i] + CONST), 7)
    S2 ← S1 ^ ROL32(A[i],12)
    T1 ← FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i]^W[i+4])
    T2 ← GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i]
    D[i+1] ← C[i]
    C[i+1] ← ROL32(B[i],9)
    B[i+1] ← A[i]
    A[i+1] ← T1
    H[i+1] ← G[i]
    G[i+1] ← ROL32(F[i], 19)
    F[i+1] ← E[i]
    E[i+1] ← P0(T2)
    CONST ← ROL32(CONST, 1)
SRCDEST.dword[3] ← A[2]
SRCDEST.dword[2] ← B[2]
SRCDEST.dword[1] ← E[2]
SRCDEST.dword[0] ← F[2]

Flags Affected

None.

Intel C/C++ Compiler Intrinsic Equivalent

VSM3RNDS2 __m128i _mm_sm3rnds2_epi32 (__m128i __A, __m128i __B, __m128i __C, const int imm8);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions.”

Source: Intel® 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes (Order Number 325462-091US, March 2026)
Generated: 7-6-2026

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