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VSM3MSG2
Henk-Jan Lebbink edited this page Jun 4, 2026
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VSM3MSG2 — Perform Final Calculation for the Next Four SM3 Message Words
| Opcode/ Instruction | Op/ En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
| VEX.128.66.0F38.W0 DA /r VSM3MSG2 xmm1, xmm2, xmm3/m128 | AV/V | AVX SM3 | Performs the final calculation for the next four SM3 message words using previous message words from xmm2 and xmm3/m128, storing the result in xmm1. |
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| A | N/A | ModRM:reg (r, w) | VEX.vvvv (r) | ModRM:r/m (r) | N/A |
The VSM3MSG2 instruction is one of the two SM3 message scheduling instructions. The instruction performs the final calculation for the next four SM3 message words.
//see the VSM3MSG1 instruction for definition of ROL32()WTMP[0] ← SRCDEST.dword[0]
WTMP[1] ← SRCDEST.dword[1]
WTMP[2] ← SRCDEST.dword[2]
WTMP[3] ← SRCDEST.dword[3]
// Dword array W[] has indices are based on the SM3 specification.
W[3] ← SRC1.dword[0]
W[4] ← SRC1.dword[1]
W[5] ← SRC1.dword[2]
W[6] ← SRC1.dword[3]
W[10] ← SRC2.dword[0]
W[11] ← SRC2.dword[1]
W[12] ← SRC2.dword[2]
W[13] ← SRC2.dword[3]
W[16] ← ROL32(W[3], 7) ^ W[10] ^ WTMP[0]
W[17] ← ROL32(W[4], 7) ^ W[11] ^ WTMP[1]
W[18] ← ROL32(W[5], 7) ^ W[12] ^ WTMP[2]
W[19] ← ROL32(W[6], 7) ^ W[13] ^ WTMP[3]
W[19] ← W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)
SRCDEST.dword[0] ← W[16]
SRCDEST.dword[1] ← W[17]
SRCDEST.dword[2] ← W[18]
SRCDEST.dword[3] ← W[19]None.
VSM3MSG2 __m128i _mm_sm3msg2_epi32 (__m128i __A, __m128i __B, __m128i __C);None.
See Table 2-21, “Type 4 Class Exception Conditions.”
Source: Intel® 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes (Order Number 325462-091US, March 2026)
Generated: 7-6-2026