VSHA512MSG2

VSHA512MSG2 — Perform a Final Calculation for the Next Four SHA512 Message Qwords

Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
VEX.256.F2.0F38.W0 CD 11:rrr:bbb VSHA512MSG2 ymm1, ymm2	AV/V		AVX SHA512	Performs the final calculation for the next four SHA512 message qwords using previous message qwords from ymm1 and ymm2, storing the result in ymm1.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	N/A	ModRM:reg (r, w)	ModRM:r/m (r)	N/A	N/A

Description

The VSHA512MSG2 instruction is one of the two SHA512 message scheduling instructions. The instruction performs the final calculation for the next four SHA512 message qwords. See https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf for more information on the SHA512 standard.

Operation

define ROR64(qword, n):
    count ← n % 64
    dest ← (qword >> count) | (qword << (64-count))
    return dest
define SHR64(qword, n):
    return qword >> n
define s1(qword):
    return ROR64(qword,19) ^ ROR64(qword, 61) ^ SHR64(qword, 6)

VSHA512MSG2 SRCDEST, SRC1

W[14] ← SRC1.qword[2]
W[15] ← SRC1.qword[3]
W[16] ← SRCDEST.qword[0] + s1(W[14])
W[17] ← SRCDEST.qword[1] + s1(W[15])
W[18] ← SRCDEST.qword[2] + s1(W[16])
W[19] ← SRCDEST.qword[3] + s1(W[17])
SRCDEST.qword[3] ← W[19]
SRCDEST.qword[2] ← W[18]
SRCDEST.qword[1] ← W[17]
SRCDEST.qword[0] ← W[16]

Flags Affected

None.

Intel C/C++ Compiler Intrinsic Equivalent

VSHA512MSG2 __m256i _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-23, “Type 6 Class Exception Conditions.”

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Source: Intel® 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes (Order Number 325462-091US, March 2026)
Generated: 7-6-2026