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Henk-Jan Lebbink edited this page Jun 4, 2026 · 1 revision

VMX INSTRUCTION REFERENCE VMXOFF — Leave VMX Operation

Opcode/ Instruction Op/En Description
0F 01 C4 VMXOFF ZO Leaves VMX operation.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
ZO NA NA NA NA

Description

Takes the logical processor out of VMX operation, unblocks INIT signals, conditionally re-enables A20M, and clears 1 any address-range monitoring.

Operation

IF (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
    THEN #UD;
ELSIF in VMX non-root operation
    THEN VMexit;
ELSIF CPL > 0 or in SEAM root operation
    THEN #GP(0);
ELSIF dual-monitor treatment of SMIs and SMM is active
    THEN VMfail(VMXOFF under dual-monitor treatment of SMIs and SMM);
    ELSE
        leave VMX operation;
        unblock INIT;
                            2
        IF IA32_SMM_MONITOR_CTL[2] = 0
            THEN unblock SMIs;
                            3
        IF outside SMX operation
            THEN unblock and enable A20M;
        FI;
        IF the processor supports SEAM
            THEN ensure that data for each active SEAM VMCS is in the memory of the corresponding VMCS region;
        FI;
        clear address-range monitoring;
        VMsucceed;
FI;

Flags Affected

See the operation section and Section 33.2.

®

  1. See the information on MONITOR/MWAIT in Chapter 11, “Multiple-Processor Management,” of the Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
  2. Setting IA32_SMM_MONITOR_CTL[bit 2] to 1 prevents VMXOFF from unblocking SMIs regardless of the value of the register’s value bit (bit 0). Not all processors allow this bit to be set to 1. Software should consult the VMX capability MSR IA32_VMX_MISC (see Appendix A.6) to determine whether this is allowed.
  3. A logical processor is outside SMX operation if GETSEC[SENTER] has not been executed or if GETSEC[SEXIT] was executed after the last execution of GETSEC[SENTER]. See Chapter 6, “Safer Mode Extensions Reference.”

33-26 Vol. 3C VMX INSTRUCTION REFERENCE

Protected Mode Exceptions

#GP(0) If executed in VMX root operation with CPL > 0. If in SEAM root operation.

#UD If executed outside VMX operation.

Real-Address Mode Exceptions

#UD The VMXOFF instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#UD The VMXOFF instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD The VMXOFF instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions

#GP(0) If executed in VMX root operation with CPL > 0. If in SEAM root operation.

#UD If executed outside VMX operation.

33-27 Vol. 3C

Source: Intel® 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes (Order Number 325462-091US, March 2026)
Generated: 7-6-2026

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