VSHA512RNDS2

VSHA512RNDS2 — Perform Two Rounds of SHA512 Operation

Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
VEX.256.F2.0F38.W0 CB 11:rrr:bbb VSHA512RNDS2 ymm1, ymm2, xmm3	AV/V		AVX SHA512	Perform 2 rounds of SHA512 operation using an initial SHA512 state (C,D,G,H) from ymm1, an initial SHA512 state (A,B,E,F) from ymm2, and a pre-computed sum of the next 2 round message qwords and the corresponding round constants from xmm3, storing the updated SHA512 state (A,B,E,F) result in ymm1.

Instruction Operand Encoding

Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
A	N/A	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	N/A

Description

The VSHA512RNDS2 instruction performs two rounds of SHA512 operation using initial SHA512 state (C,D,G,H) from the first operand, an initial SHA512 state (A,B,E,F) from the second operand, and a pre-computed sum of the next two round message qwords and the corresponding round constants from the third operand (only the two lower qwords of the third operand). The updated SHA512 state (A,B,E,F) is written to the first operand, and the second operand can be used as the updated state (C,D,G,H) in later rounds. See https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf for more information on the SHA512 standard.

Operation

define ROR64(qword, n):
    count ← n % 64
    dest ← (qword >> count) | (qword << (64-count))
    return dest
define SHR64(qword, n):
    return qword >> n
define cap_sigma0(qword):
    return ROR64(qword,28) ^ ROR64(qword, 34) ^ ROR64(qword, 39)
define cap_sigma1(qword):
    return ROR64(qword,14) ^ ROR64(qword, 18) ^ ROR64(qword, 41)
define MAJ(a,b,c):
    return (a & b) ^ (a & c) ^ (b & c)
define CH(e,f,g):
    return (e & f) ^ (g & ~e)

VSHA512RNDS2 SRCDEST, SRC1, SRC2

A[0] ← SRC1.qword[3]
B[0] ← SRC1.qword[2]
C[0] ← SRCDEST.qword[3]
D[0] ← SRCDEST.qword[2]
E[0] ← SRC1.qword[1]
F[0] ← SRC1.qword[0]
G[0] ← SRCDEST.qword[1]
H[0] ← SRCDEST.qword[0]
WK[0]← SRC2.qword[0]
WK[1]← SRC2.qword[1]
FOR i in 0..1:
    A[i+1] ← CH(E[i], F[i], G[i]) +
        cap_sigma1(E[i]) + WK[i] + H[i] +
        MAJ(A[i], B[i], C[i]) +
        cap_sigma0(A[i])
    B[i+1] ← A[i]
    C[i+1] ← B[i]
    D[i+1] ← C[i]
    E[i+1] ← CH(E[i], F[i], G[i]) +
        cap_sigma1(E[i]) + WK[i] + H[i] + D[i]
    F[i+1] ← E[i]
    G[i+1] ← F[i]
    H[i+1] ← G[i]
SRCDEST.qword[3] = A[2]
SRCDEST.qword[2] = B[2]
SRCDEST.qword[1] = E[2]
SRCDEST.qword[0] = F[2]

Flags Affected

None.

Intel C/C++ Compiler Intrinsic Equivalent

VSHA512RNDS2 __m256i _mm256_sha512rnds2_epi64 (__m256i __A, __m256i __B, __m128i __C);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-23, “Type 6 Class Exception Conditions.”

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Source: Intel® 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes (Order Number 325462-091US, March 2026)
Generated: 7-6-2026