VUnit is a unit testing framework for VHDL/SystemVerilog
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Updated
Oct 17, 2024 - VHDL
VUnit is a unit testing framework for VHDL/SystemVerilog
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
IEEE 754 single and double precision floating point library in systemverilog and vhdl
IEEE 754 single precision floating point library in systemverilog and vhdl
A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
High-Performance Binary Neural Networks for MNIST Classification: From Software to ASIC
16-bit MIPS Processor from scratch in VHDL
See beyond reality: Image super-resolution carved in silicon (FPGA Ignite 2024)
A traffic generator with AXI4 memory-mapped interface
Mi Proyecto Integrador para obtener el título de Ingeniero Electrónico. Course completion assignment for Electronic Engineer Degree.
Versatile Functional Bus Description Language compiler back-end written in Go.
Welcome to the Basys3 Library Repository! We're your go-to source for awesome hardware description language (HDL) modules. These modules help your Basys3 FPGA development board talk to and control all sorts of cool stuff. We're multilingual too, speaking HDL languages like Verilog and VHDL. Join us and let's rock the FPGA world together! 🚀
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