Quickstart guide on Icarus Verilog.

A place to keep my synthesizable verilog examples.

A completely functional encryption decryption model with specially generated Asymmetric key verification

Project to Design and Implement a 16-bit Barrel Shifter using Verilog.

Pre and Post Synthesis Simulation of a Design VSDMemSOC

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

Project to Design and Implement a 16-bit Shift Adder (Serial Adder) using Verilog.

16-bit Slansky Adder design using verilog HDL

Batchfile4iverilog

This repository consists of Load, Store and Read word data paths using a Single Cycle Core.

Verilog is a hardware description language. This repo is basically a learning journey of verilog

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments

An iverilog program displaying the working of RING and JOHNSONS counter with the Timing diagram in GTK wave.

Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

This is a simple FIFO queue implementation in Verilog for the Modern Computer Architectures course (2016-2017) of Harokopio University.

Practice Codes of Verilog Language

Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL

A repo for CS 3339 students learning verilog

A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.