HDL libraries and projects

This is a repository containing solutions to the problem statements given in HDL Bits website.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Support files for participating in a Fomu workshop

DDR2 memory controller written in Verilog

Revengineered ancient PDP-11 CPUs, originals and clones

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

Simple 8-bit UART realization on Verilog HDL.

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

All About HDL

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

Demo project for the Zero to ASIC Course.

A place to keep my synthesizable verilog examples.

An 8 input interrupt controller written in Verilog.

A simple Verilog SPI master / slave implementation featuring all 4 modes.

Collection of projects for various FPGA development boards

Project 2.2 Frequency counter

Basic UART TX/RX module for FPGA

My solution to the problem set on HDLBits.