HDL libraries and projects

Hardware Design/Visualization/Simulation/RTLGeneration Framework

A C++ to Verilog translation tool with some basic guarantees that your code will work.

This is a SpyDrNet Plugin for a physical design related transformations

Test suite designed to check compliance with the SystemVerilog standard.

A new Hardware Design Language that keeps you in the driver's seat

Sol-1: A CPU/Computer System made from 74 series logic.

ACT hardware description language and core tools.

A design of application for embedded devices, which acts as ASCII-to-morse-alphabet converter.

A huge VHDL library for FPGA development

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

Funtional verification for darkriscv.

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

Experimental cli to create HDL projects using Vivado, outside of their IDE.

Cross EDA Abstraction and Automation

TruVium HDL Development Environment