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icarus-verilog

Here are 70 public repositories matching this topic...

olofk / edalize

An abstraction library for interfacing EDA tools

Updated Nov 4, 2024
Python

mshr-h / vscode-verilog-hdl-support

HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Nov 6, 2024
TypeScript

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

unixb0y / SystemVerilogSHA256

SHA256 in (System-) Verilog / Open Source FPGA Miner

fpga bitcoin mining verilog sha256 systemverilog icarus-verilog

Updated Mar 10, 2018
SystemVerilog

dpretet / svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator surfer svut

Updated Oct 22, 2024
Python

neorv32-verilog

stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Nov 3, 2024
Verilog

scarv / xcrypto

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Jan 5, 2023
Verilog

albertxie / iverilog-tutorial

Quickstart guide on Icarus Verilog.

verilog signal icarus-verilog gtkwave csc258

Updated Jun 18, 2020
Verilog

aditeyabaral / DDCO-Lab-UE18CS207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

Updated Apr 17, 2020
Verilog

sgherbst / svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

FPGAwars / toolchain-iverilog

🌱 Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS

toolchain platformio icarus-verilog apio

Updated May 9, 2022
Verilog

librecores / docker-tools

Just a set of Dockerfiles and tools for FuseSoC

docker verilog icarus-verilog fusesoc

Updated Nov 12, 2018
Dockerfile

yasnakateb / PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm cpu verilog icarus-verilog verilog-hdl iverilog arm-processor arm-pipeline

Updated Mar 21, 2022
Verilog

TheOneKevin / icarusext

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

verilog vscode-extension icarus-verilog gtkwave verilog-testbenches

Updated Mar 4, 2023
TypeScript

ParimalaS27 / Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab

This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.

verilog prefix icarus-verilog 8bit iverilog parallel-prefixsum prefix-adder ddco

Updated Jan 6, 2021
Verilog

aditeyabaral / up-down-counter

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

counter verilog logic-programming icarus-verilog digital-design verilog-project

Updated Apr 16, 2020
Verilog

fopelite / VerilogGuides

Guides on how to install a SystemVerilog toolchain on different operating systems

systemverilog icarus-verilog

Updated Nov 23, 2023
Shell

GLADICOS / UART

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

uart icarus-verilog systemc gtkwave systemc-model uart-verilog dut

Updated Sep 27, 2022
Verilog

yasnakateb / TrafficLightController

🚦 A digital controller to control traffic in Verilog HDL

icarus-verilog traffic-light-controller

Updated Aug 12, 2019
Verilog

Elphel / vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

eclipse ide eclipse-plugin verilog vivado icarus-verilog gtkwave quartus cocotb

Updated Nov 29, 2017
Java

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