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Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.
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Dec 8, 2023 - SystemVerilog
Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
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Nov 11, 2023 - SystemVerilog
Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
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Nov 10, 2023 - SystemVerilog
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
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Jun 5, 2023 - SystemVerilog
This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques
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Sep 28, 2022 - SystemVerilog
Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL
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Jan 10, 2022 - SystemVerilog
microcircuit SLG46620 CNT/DLY2/FSM0 (from dialog semiconductor company) SystemVerilog interpretation. Dataseet is: https://www.dialog-semiconductor.com/sites/default/files/slg46620r115_10282019.pdf Simulation: QuestaSim x64 ver2020.1 Needed simulation libraries: altera_primitives (build: $projectSource/verification/altera_primitives)
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Sep 25, 2021 - SystemVerilog
SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.
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Sep 5, 2021 - SystemVerilog
A solution of test assignment from company
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Jan 7, 2020 - SystemVerilog
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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Nov 25, 2019 - SystemVerilog
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Nov 20, 2019 - SystemVerilog
SublimeText3 bits for Quartus, ModelSim, and VUnit Integration mirror of https://phabricator.kairohm.dev/diffusion/10/
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Sep 9, 2018 - SystemVerilog
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