tcl

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Here are 25 public repositories matching this topic...

adityaseelam / Projects-on-FPGA-Board-Zybo-Z7-20

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Implementing fun projects on my board.

tcl verilog

Updated Sep 18, 2024
Verilog

Pa1mantri / TCL_Workshop

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5-Day TCL begginer to advanced workshop by VSD

linux open-source tcl synthesis yosys hardware-description-language static-timing-analysis tcl-procedures opentimer

Updated Jan 24, 2024
Verilog

MoustafarRafat7 / ITI-Summer-Camp

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ITI Summer Camp Labs including :1- VHDL Lab to design a 4-bit Full Adder by 3 different styles (Behavioral - Structural- Data flow) with their testbench. 2-Verilog Labs including designing HA,FA,Decoder,Memory,UD Counter,ALU,Grey2Binary Conversations,SIPO,PISO,FSM,Sequence detectors clock dividers and Synchronous FIFO ,3-Python Labs and 4-TCL Labs.

python vhdl tcl verilog

Updated Oct 23, 2024
Verilog

bbnoir / icc

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IC Contest Practice

tcl verilog

Updated Jul 4, 2024
Verilog

Abdelrahman1810 / MIPS-Processor

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This repository contains the Verilog implementation of a MIPS processor core with pipeline, hazard solution, and exception handling, along with the corresponding testbenches.

pipeline mips assembly tcl hazard mips-architecture

Updated Jul 20, 2024
Verilog

Tarta56 / SODS_Project

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This project provides a TCL command for PrimeTime, enabling a straightforward implementation of a post-synthesis leakage power minimization procedure. Developed as part of a contest project for the course "Synthesis and Optimization of Digital Circuits" at Politecnico di Torino. This tool is designed to streamline power optimization efforts.

tcl primetime

Updated Nov 2, 2023
Verilog

Dany2002-hub / Vivado_Scripting_and_Automation

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ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Verilog/SystemVerilog modules and finally generating a CSV file containing several components of the generated power, timing, and utilization reports.

python shell automation scripting jupyter-notebook tcl verilog vivado systemverilog

Updated Mar 11, 2023
Verilog

Azizabdultushar / irdropanalysis

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IR drop analysis is a critical step in digital design, focusing on the potential difference (voltage drop) between two points in a conducting wire due to its resistance. This phenomenon, described by Ohm's Law (V=IR), can significantly impact the performance of integrated circuits (IC).

script tcl cadence ir-drop voltage-drop-analysis

Updated Nov 1, 2024
Verilog

Luca-Dalmasso / LL_contest

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Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT

vhdl tcl synopsys cmos low-power digital-electronics asic-design

Updated Jul 11, 2021
Verilog

saivittalb / simd-processor-verification

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✅ Formal verification of a 16-bit SIMD processor

linux makefile tcl verilog systemverilog questa systemverilog-assertions questa-propcheck

Updated Feb 1, 2023
Verilog

Visruat / VSD-TCL

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TCL Script automating the frontend of ASIC design

tcl synthesis static-timing-analysis asic-design

Updated Jun 21, 2023
Verilog

thegabriele97 / TCL-Learning

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Contains some TCL scriping language excercises + 2 university contests on HIgh Level Synthesis (winner contest) and Logic Level Synthesis

tcl

Updated Jul 10, 2021
Verilog

andrea4g / low_power_contest

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Master degree project for Synthesis and Optimization of Digital Systems

optimization polito tcltk tcl synthesis synopsys low-power

Updated Feb 16, 2018
Verilog

AkshayXPatil / MSDAP

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Complete design of a Mini Stereo Digital Audio Processor

asic perl scripting tcl rtl convolution fir-filter gdsii

Updated Jan 3, 2019
Verilog

Luca-Dalmasso / RISCV_LBIST

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Scan insertion and design of a LBIST wrapper for a RISC-V core for stuck-at fault model

asic vhdl tcl riscv hardware-testing design-for-testability atpg rtl-design

Updated Jan 17, 2022
Verilog

gabrielganzer / VHDL-DesignSynthesis

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Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

polito vhdl scripts tcl rtl verilog synthesis digital-design control-unit subtractor physical-design booth-multiplier register-file windowed-register-file adder-subtractor

Updated Jan 24, 2021
Verilog

gabrielganzer / RTL-PowerOptimization

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Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.