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tcl

Here are 21 public repositories matching this topic...

bbnoir / icc

IC Contest Practice

Updated May 15, 2024
Verilog

Tarta56 / SODS_Project

This project provides a TCL command for PrimeTime, enabling a straightforward implementation of a post-synthesis leakage power minimization procedure. Developed as part of a contest project for the course "Synthesis and Optimization of Digital Circuits" at Politecnico di Torino. This tool is designed to streamline power optimization efforts.

Updated Nov 2, 2023
Verilog

Dany2002-hub / Vivado_Scripting_and_Automation

ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Verilog/SystemVerilog modules and finally generating a CSV file containing several components of the generated power, timing, and utilization reports.

python shell automation scripting jupyter-notebook tcl verilog vivado systemverilog

Updated Mar 11, 2023
Verilog

saivittalb / simd-processor-verification

✅ Formal verification of a 16-bit SIMD processor

linux makefile tcl verilog systemverilog questa systemverilog-assertions questa-propcheck

Updated Feb 1, 2023
Verilog

Luca-Dalmasso / RISCV_LBIST

Design of a BIST module for RISC-V fault testing

asic vhdl tcl riscv hardware-testing atpg rtl-design

Updated Jan 17, 2022
Verilog

Pa1mantri / TCL_Workshop

5-Day TCL begginer to advanced workshop by VSD

linux open-source tcl synthesis yosys hardware-description-language static-timing-analysis tcl-procedures opentimer

Updated Jan 24, 2024
Verilog

Visruat / VSD-TCL

TCL Script automating the frontend of ASIC design

tcl synthesis static-timing-analysis asic-design

Updated Jun 21, 2023
Verilog

Luca-Dalmasso / LL_contest

Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT

vhdl tcl synopsys cmos low-power digital-electronics asic-design

Updated Jul 11, 2021
Verilog

thegabriele97 / TCL-Learning

Contains some TCL scriping language excercises + 2 university contests on HIgh Level Synthesis (winner contest) and Logic Level Synthesis

tcl

Updated Jul 10, 2021
Verilog

AkshayXPatil / MSDAP

Complete design of a Mini Stereo Digital Audio Processor

asic perl scripting tcl rtl convolution fir-filter gdsii

Updated Jan 3, 2019
Verilog

andrea4g / low_power_contest

Master degree project for Synthesis and Optimization of Digital Systems

optimization polito tcltk tcl synthesis synopsys low-power

Updated Feb 16, 2018
Verilog

gabrielganzer / VHDL-DesignSynthesis

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

polito vhdl scripts tcl rtl verilog synthesis digital-design control-unit subtractor physical-design booth-multiplier register-file windowed-register-file adder-subtractor

Updated Jan 24, 2021
Verilog

f4pga-xc-fasm2bels

chipsalliance / f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

tcl verilog vivado fasm bitstream artix-7 symbiflow

Updated Sep 25, 2023
Verilog

gabrielganzer / RTL-PowerOptimization

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

script optimization polito tcl project synopsys dvs primetime voltage-scaling design-vision synopsys-dc

Updated Jun 9, 2021
Verilog

addisonElliott / SCIC

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

asic cpu digital simulation tcl rtl verilog synthesis icarus-verilog gate cadence

Updated Nov 29, 2018
Verilog

fayizferosh / yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools

Updated Oct 18, 2023
Verilog

AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

fpga cpp matlab tcl verilog

Updated Jul 21, 2023
Verilog

RomeoMe5 / DDLM

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Updated Sep 15, 2023
Verilog

The-OpenROAD-Project / OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Jun 13, 2024
Verilog

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Jun 13, 2024
Verilog

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