wiring jtag debug

JTAG: TCK, TMS, TDI and TDO

Understand the four core JTAG signals and their direction at a target.

Applies to: Single-target signal diagram. Pin order, voltage and optional reset signals depend on the exact probe and connector.

When to use it

Using supported programming, debugging or boundary-scan tools with documented target hardware.

Why it works this way

Separate clock, state control and serial input/output let a probe communicate with a target's test-access port.

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Connection reference

Target signal	Direction at target	Purpose
TCK	Input	Clock
TMS	Input	State selection
TDI	Input	Serial data in
TDO	Output	Serial data out

Make the connection

1. Match the target connector and I/O voltage; identify optional nTRST and system reset separately.
2. For multiple targets, use the documented chain order and instruction-register configuration.

Check before powering

• Do not assume that a similarly sized header is JTAG.
• Do not connect a probe's power-output contact unless the board and probe documentation explicitly allow it.

Matching module references

This is a general interface guide; match your own hardware documentation.

Sources & review

Source documents inspected; independent electrical and bench review pending. Reviewed 2026-09-27.

• SEGGER: J-Link interface description — 20-pin JTAG signal direction and VTref; checked 2026-09-27

Original writing and diagram by Kal / Valleytech Solutions, CC BY 4.0. Manufacturer artwork and documentation retain their own rights.

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