This repository hosts the code for an FPGA based accelerator for convolutional neural networks

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

An introduction to integrated circuit design with Verilog and the Papilio Pro development board.

Router 1 x 3 verilog implementation

EE4415 Project : AES Verilog

RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.

Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.

UART - RTL Design and Verification

An NPU designed using an LLM with a single prompt

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with sigle port sync RAM. The project includes the design and code for an SPI Slave, a single-port asynchronous RAM, and an SPI Wrapper that connects the RAM and SPI Slave.

Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract

SUSTech CS207 Digital Design 2018Fall Materials.

Sample Verilog codes for digital circuits

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

booth's multiplier defined by datapath and control path , where controller generates different control signals which are used by different modules to generate product

Single and double precision floating point unit implemented using Verilog HDL