Documenting the Xilinx 7-series bit-stream format.

An abstraction library for interfacing EDA tools

[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.

A Python package to use FPGA development tools programmatically.

Limited python / cocotb interface to Xilinx/AMD Vivado simulator.

HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

Bazel rules for Xilinx Vivado

A flexible and scalable development platform for modern FPGA projects.

Example of how to get started with olofk/fusesoc.

A Cadence Allegro PCB schematics parser and verification tool. Together with IBERTpy can configure, run, and compile Vivado IBERT eye diagrams using information from Cadence Allegro schematics.

A Python package for running IBERT Eye scan in Vivado, ploting eye diagrams with mathplotlib and compiling results with LaTeX

Visual System Integrator - Accelerate your embedded development

This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

Scripts to automate downloads of Vivado/Vitis binaries from the AMD Xilinx website without the need of a GUI.