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vivado

Here are 31 public repositories matching this topic...

hdl-util / hdmi

Send video/audio over HDMI on an FPGA

audio video fpga intel xilinx vivado altera hdmi systemverilog dvi quartus hdlmake

Updated Feb 3, 2024
SystemVerilog

tymonx / logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

f4pga / prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

fpga xilinx vivado fuzzer xilinx-fpga bitstream ultrascale symbiflow ultrascale-plus

Updated Feb 9, 2022
SystemVerilog

tymonx / virtio

Virtio implementation in SystemVerilog

cmake fpga model rtl verilog xilinx vivado systemverilog systemc hdl virtio verilator quartus

Updated Jan 23, 2018
SystemVerilog

sgherbst / svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

agicy / buptLab-digital_design

北京邮电大学 2023-2024 春季学期《数字逻辑与数字系统课程设计》——电子钟、药片装瓶系统和贪吃蛇

vivado systemverilog bupt digital-design artix7

Updated Aug 31, 2024
SystemVerilog

meiniKi / logIP

Logic Analyzer IP Core

asic fpga digital amd ip verilog xilinx vivado ols systemverilog measurements hdl formal-verification basys3 hardware-description-language logicanalyzer sump logip symbiyosys

Updated Jul 23, 2022
SystemVerilog

Luke7412 / IpLibrary

Library containing various VHDL IPs

rtl ip xilinx vivado ip-xact systemverilog ipxact arty-a7 packaged-ip

Updated Jan 5, 2024
SystemVerilog

angrammenos97 / imc

In-Memory Accelerator Controller

controller vivado systemverilog hdl questasim risc-v edge-computing in-memory-computing pulpissimo

Updated Sep 13, 2024
SystemVerilog

erwanregy / Neural-Network-on-an-FPGA

Fully connected dense neural network in SystemVerilog, synthesisable to an FPGA for neural network computation acceleration

fpga neural-network rtl xilinx vivado zynq-7000

Updated Mar 15, 2023
SystemVerilog

dsa-shua / FPGA-SystolicArray

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

sdk fpga hardware accelerator matrix project matrix-multiplication verilog xilinx vivado systemverilog hardware-designs hdl hardware-acceleration zynq-7000 systolic-arrays pynq-z2 vitis

Updated Feb 16, 2024
SystemVerilog

JochiSt / AI_FPGA

running ANN on an FPGA

machine-learning fpga neural-network vivado vivado-hls hls4ml

Updated Jan 11, 2023
SystemVerilog

34-Engineering / Virtex-HDL

This repository contains the Xilinx Vivado project for the Artix-7 (XC7A35T-1FTG256C) FPGA on Virtex.

fpga vivado systemverilog artix-7

Updated Jul 9, 2022
SystemVerilog

dpavlo55 / vhdl-vga-controller

VHDL implementation of VGA controller. Implemented on Zybo Zynq-7000 board which uses switches to change output color.

vhdl vivado zybo zynq-7000 vga-controller

Updated May 12, 2019
SystemVerilog

2uger / petalinux_notes

Notes after working with Zynq platform using vivado and petalinux

linux xilinx vivado systemverilog soc petalinux dma zynq-7000 axi-stream

Updated Feb 26, 2024
SystemVerilog

ufukpalpas / Cellular-automata-game

An cellular automata game for a 8x8 matrix on the BetiBoard. (requires Basys3 board)

cellular-automata xilinx vivado systemverilog basys3 basys3-fpga

Updated Mar 20, 2020
SystemVerilog

PongGameVerilog

jideoyelayo1 / PongGameVerilog

A Pong Game made in Verilog

fpga vivado pingpong nexys4ddr

Updated May 16, 2023
SystemVerilog

muhammadtalhasami / Axi4_lite_interface

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

vivado system-verilog verilator axi4 axi4-lite axi4-protocol axi4-lite-interface axi4-lite-system-verilog

Updated May 4, 2024
SystemVerilog

atticusrussell / MIPS

A pipelined MIPS microprocessor written in VHDL and simulated in Xilinx Vivado targeting Basys3 board. Simplified MIPS instruction set. Made in RIT DSD2 (CMPE-260).

fpga mips processor vhdl vivado clock-speed dsd2

Updated Jun 12, 2023
SystemVerilog

JacobLondon / tea-encryption

Tea Encryption for ECE 4304 VHDL Design Project

school vhdl tea vivado uart vga blockcipher

Updated Dec 9, 2019
SystemVerilog

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