[ExecuTorch][WebGPU] Add linear_qcs4w op (et_vk.linear_qcs4w)#21211
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[ExecuTorch][WebGPU] Add linear_qcs4w op (et_vk.linear_qcs4w)#21211JCNTH wants to merge 1 commit into
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21211
Note: Links to docs will display an error until the docs builds have been completed. ❗ 1 Active SEVsThere are 1 currently active SEVs. If your PR is affected, please view them below: ❌ 46 New Failures, 3 Unrelated FailuresAs of commit cc9e073 with merge base 266e0dc ( NEW FAILURES - The following jobs have failed:
FLAKY - The following jobs failed but were likely due to flakiness present on trunk:
BROKEN TRUNK - The following job failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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This was referenced Jul 22, 2026
This was referenced Jul 22, 2026
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Approving full WebGPU stack
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Stack from ghstack (oldest at bottom):
Problem: The WebGPU delegate has no
et_vk.linear_qcs4w— a 4-bit channels-symmetric-weight linear (per-output-channel symmetric weight, no zero-point). It is reachable via theVulkanQuantizerweight-only 4-bit path (distinct from the XNNPACK static-PT2E path that produces the q8ta ops), but had no WebGPU handler.Solution: Port
et_vk.linear_qcs4w(fp32 activation, int4 weight), mirroring the landedlinear_q4gswregister-tiled buffer GEMM (quantized_linear/QuantizedLinear.cpp+q4gsw_linear.wgsl) simplified to per-channel scale. Vulkan ref:impl/QuantizedLinearQCSNW.cpplinear_qcs4w(check_linear_qcsnw_args: args[mat1, qmat2=[N,K/2] 4-bit, scales=[N], out], symmetric per-output-channel, no group, no zero-point, no bias) +glsl/linear_qcsnw_coop.glsl. Before/After vs q4gsw: q4gsw scale is groupedscales[(k/group_size)*padded_N + n]; qcs4w scale is per-channelscales[n](1D [N]) — no group_size, no padded_N, no bias.Implementation:
linear_qcs4w/QuantizedLinearQcs4w.cppregisterset_vk.linear_qcs4w->qcs4w_linear_impl, args[in, weight, scales, out](out=args.back()).qcs4w_linear.wgsl: register-tiled (TM=TN=4) GEMM,acc += in[m,k] * (unpack_int4(w) - 8) * scales[n], 2D-folded dispatch (lifts the 65535 cap).Qcs4wParams(16 bytes: M/N/K/K_packed) matches the WGSL Params. Guards fp32 in/out,K_packed==ceil(K/2),N*K_packed%4==0(u32-packed),scales>=N, all fail-loud. Resize hook recomputes live M + dispatch.Constraints / divergences from the Vulkan reference: (1) buffer re-derivation of Vulkan's texture-based qcs4w GEMM (WebGPU always buffers). (2) CRITICAL — nibble order: the qcs4w AOT packer (
_passes/fuse_quantized_ops.py) stores(even_col<<4)|odd_col, the SWAP of q4gsw'spack_4bit_weight_tensor(odd<<4)|even— so this kernel reads even-k from the HIGH nibble and odd-k from the LOW nibble, the reverse ofq4gsw_linear.wgsl(verified against the packer, the Vulkanlinear_qcsnw_coop.glslunpack, and a byte-search of the served.pte). (3)+8-shifted int4 recovered as signed[-8,7](same as q4gsw). (4) one tiled kernel only (q4gsw's GEMV/shmem perf variants are separate, Canary-gated follow-ups). Bias is out of the op (a Linear bias lowers to a separateaten.add).Differential Revision: D112257623