[ExecuTorch][WebGPU] Add linear_q8ta_q8csw op (et_vk.linear_q8ta_q8csw)#21213
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[ExecuTorch][WebGPU] Add linear_q8ta_q8csw op (et_vk.linear_q8ta_q8csw)#21213JCNTH wants to merge 1 commit into
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21213
Note: Links to docs will display an error until the docs builds have been completed. ❗ 1 Active SEVsThere are 1 currently active SEVs. If your PR is affected, please view them below: ❌ 46 New Failures, 3 Unrelated FailuresAs of commit 9984323 with merge base 266e0dc ( NEW FAILURES - The following jobs have failed:
FLAKY - The following jobs failed but were likely due to flakiness present on trunk:
BROKEN TRUNK - The following job failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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This was referenced Jul 22, 2026
This was referenced Jul 22, 2026
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Approving full WebGPU stack
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Stack from ghstack (oldest at bottom):
Problem: The WebGPU delegate has no
et_vk.linear_q8ta_q8csw— an int8-activation x int8-channelwise-weight linear with a FP32 output (the "output-not-requantized" sibling of the landedq8ta_linear, e.g. a final projection). Its kernel design was ready but it was thought unreachable; the reachability blocker is now solved.Solution: Port
et_vk.linear_q8ta_q8csw(int8 x, int8 per-channel weight, fp32 out), mirroring the landedq8ta_linear(q8ta_linear/Q8taLinear.cpp) with the output requant removed. Before/After vsq8ta_linear: same i32 GEMMΣ(x_int8 - input_zp) * w_int8+ dequant* input_scale * weight_scales[n] + bias, butq8ta_linearthen requantizes to int8 (needs output_scale/zp, N%4==0 for output packing) whereas this writes fp32 directly (no output qparams in the schema, N unconstrained). Mirrors Vulkanimpl/QuantizedLinear.cpplinear_q8ta_q8csw.Implementation:
linear_q8ta_q8csw/LinearQ8taQ8csw.cppregisterset_vk.linear_q8ta_q8csw->linear_q8ta_q8csw_impl. Schema[x, input_scale, input_zp, weights, weight_sums, weight_scales, bias?, out]: x/weights int8 (boundarray<u32>, unpacked in-shader),weight_sums(arg 4) folded per-element (unused, matching q8ta_linear),out=args.back().linear_q8ta_q8csw.wgslregister-tiled (TM=TN=4) i32 GEMM, 2D-folded dispatch; the TN=4 tile guardsn<N(no N%4 assumption — fp32 output has no packing constraint).Q8taQ8cswParams(32 bytes) matches the WGSL Params. Guards int8 x/weight (numel%4==0 for the u32 reads), fp32 out, scales fp32 [N], all fail-loud.Constraints / divergences from the Vulkan reference: fp32 output only. A bias-less TERMINAL linear can mis-fuse to an int8 output the schema cannot compute (no output scale/zp) — the handler fail-louds on it (
output must be fp32); the correct fp32-out form is what the fusion routes when the output is not re-quantized. i32 accumulator (inherited from q8ta_linear). Buffer-only, so no int8x4 texture layout.Differential Revision: D112257666