[ExecuTorch][WebGPU] Add bitwise_and + bitwise_not ops (bool)#21223
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[ExecuTorch][WebGPU] Add bitwise_and + bitwise_not ops (bool)#21223JCNTH wants to merge 1 commit into
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21223
Note: Links to docs will display an error until the docs builds have been completed. ❗ 1 Active SEVsThere are 1 currently active SEVs. If your PR is affected, please view them below: ❌ 46 New Failures, 3 Unrelated FailuresAs of commit 6413b43 with merge base 266e0dc ( NEW FAILURES - The following jobs have failed:
FLAKY - The following jobs failed but were likely due to flakiness present on trunk:
BROKEN TRUNK - The following job failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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This was referenced Jul 22, 2026
This was referenced Jul 22, 2026
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Approving full WebGPU stack
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Stack from ghstack (oldest at bottom):
Adds the two bool bitwise ops the Vulkan partitioner tags (
op_registry.pymarksbitwise_and.Tensor,bitwise_not.default,logical_and.defaultallBOOL_T).bitwise_andon bool is identical tological_and, so it shares the one AND handler — mirroring Vulkan, which registers bothaten.bitwise_and.Tensorandaten.logical_and.defaultto itsbitwise_andhandler (BinaryOp.cpp:160-161). No new kernel needed.bitwise_notis the bool NOT: Vulkan uses1 - Xon uint8 (unary_op.yaml); for canonical 0/1 that equals a per-byte low-bit flip, so the packed-word kernel ist_out[w] = t_a[w] ^ 0x01010101u(one thread per word).Key changes:
runtime/ops/logical_and/LogicalAnd.cpp— registeraten.bitwise_and.Tensoron the existing shared bool-AND handler.runtime/ops/bitwise_not/{BitwiseNot.cpp,bitwise_not.wgsl}— new unary; out (rw) + a (ro) + params (uniform); fail-loud bool-dtype/null/same-shape guards; resize hook re-appliesnum_words.CMakeLists.txt— registerBitwiseNot.cpp.Bool only (
numel % 4 == 0for the packed bindings), matching the backend's other bool ops.Co-authored-with: Claude Code.
Differential Revision: D112257647