[ExecuTorch][WebGPU] Add logical_and op (aten.logical_and.default)#21221
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[ExecuTorch][WebGPU] Add logical_and op (aten.logical_and.default)#21221JCNTH wants to merge 1 commit into
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21221
Note: Links to docs will display an error until the docs builds have been completed. ❗ 1 Active SEVsThere are 1 currently active SEVs. If your PR is affected, please view them below: ❌ 46 New Failures, 3 Unrelated FailuresAs of commit 1ff68a8 with merge base 266e0dc ( NEW FAILURES - The following jobs have failed:
FLAKY - The following jobs failed but were likely due to flakiness present on trunk:
BROKEN TRUNK - The following job failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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This was referenced Jul 22, 2026
This was referenced Jul 22, 2026
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Approving full WebGPU stack
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Stack from ghstack (oldest at bottom):
Adds the elementwise bool
aten.logical_and.defaultto the WebGPU delegate. Vulkan maps this op to itsbitwise_andhandler (BinaryOp.cpp:161), valid for canonical 0/1 bool bytes; this port mirrors that. Both operands and the output are 1-byte bool tensors packed 4/word intoarray<u32>, so a word-wise AND is exactly a per-byte AND.Key changes:
runtime/ops/logical_and/logical_and.wgsl— one thread per packed word,t_out[w] = t_a[w] & t_b[w](2D-folded dispatch).runtime/ops/logical_and/LogicalAnd.cpp— handler binds out (rw) + a/b (ro) + params (uniform); fail-loud guards on bool dtype, null buffer, and same-shape; resize hook re-appliesnum_words+ dispatch.CMakeLists.txt— register the op source.Same-shape only (
numel % 4 == 0for the packed bool bindings), matching the backend's other bool ops.Co-authored-with: Claude Code.
Differential Revision: D112257653