BitCap IPReporter is a cross-platform IP Reporter tool for Bitmain, Whatsminer, IceRiver ASICs

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

A simplified and standardized interface for Bitcoin ASICs.

Efficient Library software for Miners and Pools

Structural Netlist API (and more) for EDA post synthesis flow development

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Allo: A Programming Model for Composable Accelerator Design

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

Haskell to VHDL/Verilog/SystemVerilog compiler

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

VUnit is a unit testing framework for VHDL/SystemVerilog

Материалы для курсов "Введение в проектирование на языке Verilog" (2024+), "Введение в FPGA и Verilog" (2018-2019)

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Berkeley's Spatial Array Generator

Package manager and build tool for HDLs

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

TinyTapeout submission with the AY-3-8913 a 3-voice programmable sound generator (PSG) chip from General Instruments.

TinyTapeout submission with the SN76489 Digital Complex Sound Generator (DCSG) programmable sound generator (PSG) chip from Texas Instruments.

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

A huge VHDL library for FPGA development