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174 public repositories
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HDL libraries and projects
Updated
Sep 12, 2024
Verilog
This is a repository containing solutions to the problem statements given in HDL Bits website.
Updated
Jul 16, 2023
Verilog
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Updated
Apr 30, 2024
Verilog
Support files for participating in a Fomu workshop
Updated
Mar 17, 2024
Verilog
Custom chips reverse-engineered from silicon
Updated
Aug 2, 2024
Verilog
Revengineered ancient PDP-11 CPUs, originals and clones
Updated
Aug 31, 2024
Verilog
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
Updated
Oct 31, 2023
Verilog
Simple 8-bit UART realization on Verilog HDL.
Updated
Apr 27, 2024
Verilog
DDR2 memory controller written in Verilog
Updated
Feb 28, 2012
Verilog
An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
Updated
May 2, 2019
Verilog
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
Updated
Nov 25, 2020
Verilog
Collection of projects for various FPGA development boards
Updated
May 13, 2024
Verilog
Updated
Aug 21, 2019
Verilog
A simple Verilog SPI master / slave implementation featuring all 4 modes.
Updated
Dec 7, 2020
Verilog
A place to keep my synthesizable verilog examples.
Updated
Jul 10, 2023
Verilog
Wrappers for open source FPU hardware implementations.
Updated
Apr 10, 2024
Verilog
Basic UART TX/RX module for FPGA
Updated
Oct 18, 2018
Verilog
💻 Build own computer by fpga.
Updated
Jun 9, 2022
Verilog
An 8 input interrupt controller written in Verilog.
Updated
Mar 22, 2012
Verilog
KISCV, a KISS principle riscv32i CPU
Updated
Aug 16, 2024
Verilog
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