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hdl

Here are 21 public repositories matching this topic...

metroboy

aappleby / metroboy

A repository of gate-level simulators and tools for the original Game Boy.

emulator simulator gameboy gameboy-emulator verilog hdl

Updated Nov 14, 2024
C++

Kitware / VeloView

VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.

lidar velodyne-sensor velodyne sensor-data hdl lidar-measurements lidar-data-manipulation lidar-camera-calibration velodyne-hdl-sensors sensor-streaming

Updated Sep 29, 2021
C++

kactus2 / kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

design fpga hardware eda ip-xact reuse hdl mpsoc system-on-chip

Updated Oct 21, 2024
C++

aappleby / metron

A C++ to Verilog translation tool with some basic guarantees that your code will work.

c fpga compiler cpp transpiler verilog hdl

Updated Nov 13, 2024
C++

asyncvlsi / act

ACT hardware description language and core tools.

language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes

Updated Nov 11, 2024
C++

eclufsc / ophidian

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

open-source design automation embedded research cpp vhdl cpp14 eda teaching cpp11 verilog cpp17 hdl data-driven-design physical-design

Updated Feb 17, 2021
C++

lethalbit / discretize

A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad

electronics verilog hdl yosys-plugin

Updated Jan 15, 2024
C++

donn / Phi

Hardware description language that tries not to suck

fpga eda verilog compilers systemverilog hdl phi

Updated Oct 29, 2022
C++

Goshik92 / FpgaCha

Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)

arm cryptography encryption fpga verilog altera systemverilog hdl soc chacha20 dma cyclone-v ip-core hps rfc7539 platform-designer rfc8439

Updated Jul 29, 2020
C++

trcwm / fptool

Compiler for generating fixed-point logic using VHDL

signal-processing vhdl arithmetic fixed-point hdl

Updated Jun 20, 2024
C++

danielvieiravega / VcdParser

Value Change Dump (VCD) File parser

vhdl verilog simulations hdl vcd value-change-dump

Updated May 21, 2017
C++

TILhub / SystemC-Introduction

SystemC is a set of C++ classes and macros which provide an event-driven simulation interface (see also discrete event simulation). These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax.

c system cpp cplusplus-14 threads systemc hdl verilog-hdl oops-in-cpp

Updated Oct 7, 2018
C++

jeudine / Mersenne-twister-hardware

A flexible hardware module written in SystemVerilog which implements the Mersene twister (using a 32-bit word length). A simulation and a test bench written in SystemC, which uses Verilator were created in order to verify the correctness and to measure performance of the hardware module.

hardware random-number-generators systemverilog systemc hdl verilator

Updated Jan 10, 2021
C++

omasanori / veriwell

A Verilog (IEEE 1364-1995) simulator

simulation verilog hdl verilog-hdl

Updated Jul 5, 2023
C++

zslwyuan / gem5-HDL_v1.0

gem5-HDL_v1.0

fpga verilog hdl gem5

Updated Oct 20, 2018
C++

mckidder / Playground

Testing area for exploration!

elisp data-structures alu hdl mips32

Updated Nov 29, 2018
C++

rjb32 / verilog-simple

Example of a simple Verilog module with a C++ test bench using Verilator.

cpp verilog hdl verilator

Updated May 12, 2019
C++

Lab1-Counter

clemenkok / Lab1-Counter

I love SystemVerilog

riscv systemverilog hdl

Updated Nov 3, 2022
C++

aitesam961 / lynx-VTL

A codebase for learning effective use of verilator

fpga simulation verilog systemverilog hdl verilator

Updated Dec 10, 2023
C++

mssola / hdl

Playing around with Hardware Description Languages.

verilog systemverilog hdl

Updated Jul 10, 2024
C++

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