processor
Here are 99 public repositories matching this topic...
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…
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Jul 17, 2022 - Verilog
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
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Dec 2, 2019 - Verilog
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
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Jan 17, 2018 - Verilog
A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
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Jul 4, 2019 - Verilog
SystemOT, yet another home brew cpu.
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Aug 9, 2022 - Verilog
RISC V core implementation using Verilog.
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Mar 27, 2021 - Verilog
Super scalar Processor design
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Sep 7, 2014 - Verilog
This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction scheduling.
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May 14, 2021 - Verilog
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